Adjustable clock and power gating control

A method, comprising:

• receiving, by a computing device, operating parameters associated with a plurality of heterogeneous client circuits, wherein the plurality of heterogeneous client circuits is configured to access a memory resource circuit via a memory controller circuit, the memory controller circuit coupled to the memory resource circuit and coupled to the plurality of client circuits;
• determining, by the computing device and based on the operating parameters, a threshold power state for the memory resource circuit;
• initiating, by the computing device, a clock gating operation, a power gating operation, or both for the memory resource circuit;
• and
• maintaining, by the computing device, at least the threshold power state for the memory resource circuit, wherein maintaining the at least the threshold power state includes limiting performance of the clock gating operation, the power gating operation, or both for the memory resource circuit.

A system, comprising:

• a memory resource circuit;
• a memory controller circuit coupled to the memory circuit and coupled to a plurality of heterogeneous client circuits;
• and
• a power management circuit coupled to the memory controller circuit, wherein the power management circuit is configured to:
• receive operating parameters associated with the plurality of client circuits,
• determine, based on the operating parameters, a threshold power state for the memory resource circuit, and
• initiate a clock gating operation, a power gating operation, or both for the memory resource circuit, including to maintain at least the threshold power state for the memory resource circuit.