Display substrate and display device

A display substrate, comprising:

• a base substrate;
• a driving circuit layer comprising pixel units arranged in an array form, at least one of the pixel units comprising a plurality of sub-pixels, wherein at least one of the sub-pixels comprises a pixel driving circuit, and the pixel driving circuit comprises a light-emitting element, a plurality of transistors and a storage capacitor;
• the plurality of transistors comprises a first transistor and a second transistor, and the first transistor is coupled to the second transistor;
• a plurality of scanning lines, wherein the plurality of scanning lines comprises a first scanning line and a second scanning line, both the first scanning line and the second scanning line extend along a first direction and are arranged along a second direction, the first direction is an extension direction of sub-pixels in a row, and the second direction is an extension direction of sub-pixels in a column;
• wherein the plurality of transistors comprises one or more active patterns, and an active pattern of each transistor comprises a channel region and a conductive region, wherein an active pattern of the first transistor comprises a first channel region, an active pattern of the second transistor comprises a second channel region, the first channel region is located on a side of the first scanning line away from the second scanning line, and the second channel region is located on a side of the second scanning line away from the first scanning line;
• wherein the display substrate further comprises a plurality of signal lines;
• the plurality of signal lines comprises a first signal line and a second signal line;
• the first signal line is coupled to a first electrode of the first transistor;
• the second signal line is coupled to a first electrode of the second transistor;
• the first transistor is configured to transmit a voltage signal of the first signal line to a second electrode of the first transistor under control of a first scanning line signal;
• the second transistor is configured to transmit a voltage signal of the second signal line to a second electrode of the second transistor under control of a second scanning line signal;
• the second electrode of the first transistor and the second electrode of the second transistor are coupled to a first node;
• wherein the plurality of scanning lines further comprises a third scanning line, and the plurality of signal lines further comprises a power source line;
• the third scanning line comprises a first branch scanning line extending along the first direction and a second branch scanning line extending along the second direction, the first branch scanning line is coupled to the second branch scanning line;
• the plurality of transistors further comprises a third transistor and a driving transistor;
• the storage capacitor comprises a first electrode plate and a second electrode plate;
• a second electrode of the third transistor, a gate electrode of the driving transistor and the first electrode plate of the storage capacitor are coupled to a second node, a gate electrode of the third transistor is coupled to the third scanning line, and a first electrode of the third transistor is coupled to the first node;
• the third transistor is configured to transmit a voltage of the first node to the second node under control of a third scanning line signal;
• for sub-pixels in a same row, the first branch scanning line is located on the side of the first scanning line away from the second scanning line.