Reset circuit and timing controller including the same

A reset circuit, comprising:

• a low voltage detecting circuit configured to receive a power signal and output a low voltage reset signal, the low voltage detecting circuit comprising:
• a first cell comprising a tie-high cell among standard cells;
• at least one second cell comprising a delay cell among the standard cells;
• and
• a third cell configured to output the low voltage reset signal by receiving all signals outputted from the first cell and the at least one second cell.

A timing controller, comprising:

• a control signal generating circuit configured to generate a data control signal and a gate control signal based on timing signals received from an external system;
• a video signal converting circuit configured to convert and output a video signal received from the external system;
• and
• a reset circuit configured to reset the control signal generating circuit and the video signal converting circuit by receiving a power signal and an external reset signal and outputting an internal reset signal to at least one of the control signal generating circuit or the video signal converting circuit, the reset circuit comprising:
• a low voltage detecting circuit configured to receive a power signal and output a low voltage reset signal, the low voltage detecting circuit comprising:
• a first cell configured to receive the power signal and output a voltage corresponding to logic “0” based on the power signal being smaller than a threshold voltage or a voltage corresponding to logic “1” based on the power signal being greater than the threshold voltage;
• at least one second cell connected in series to the first cell and configured to output a signal inputted from the first cell after delaying the signal for a predetermined delay time;
• and
• a third cell configured to output the low voltage reset signal by receiving all signals outputted from the first cell and the at least one second cell.