Physical verification workflow for semiconductor circuit designs

A method for physical verification of workflow for semiconductor circuit designs, the method comprising:

• splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores;
• extracting parasitic capacitance structures from the IC layout;
• generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed;
• and
• extracting parasitic resistance structures from the IC layout.

A system for physical verification of a semiconductor circuit design, the system comprising:

• a computing device including a plurality of central processing cores;
• electronic design automation (EDA) tool operable to run on the computing device, the EDA tool including:
• a splitting module operable to split an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores;
• a parasitic capacitance module operable to extract for each window parasitic capacitance structures from the IC layout;
• a fill element module operable to generate for each window fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed;
• and
• a parasitic resistance module operable to extract for each window parasitic resistance structures from the IC layout.