Temperature margin setting method for 3D integrated circuit

A method of setting a temperature margin when designing a 3D (three-dimensional) integrated circuit, the method comprising:

• generating a first distance-delay table with respect to a first chip, based on a thermal analysis result;
• generating a second distance-delay table with respect to a second chip stacked on top of the first chip, based on the thermal analysis result;
• calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path;
• setting a temperature margin with respect to the first timing path based on the first distance-delay table and the first timing path distance;
• calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path;
• and
• setting a temperature margin with respect to the second timing path based on the second distance-delay table and the second timing path distance.

An apparatus of designing a 3D integrated circuit including a processor and a memory device, the apparatus comprising:

• the processor is configured to load a design tool into the memory device and execute the design tool that is loaded, and
• wherein the design tool includes:
• a thermal analysis tool configured to generate a distance-delay table with respect to at least one of a first chip and a second chip stacked on the first chip, based on a thermal analysis result;
• and
• a static timing analysis tool configured to respectively calculate a first timing path distance corresponding to the first chip and a second timing path distance corresponding to the second chip in a 3D signal transfer path, and to set a temperature margin with respect to the 3D signal transfer path based on the first and second timing path distances and the distance-delay table.