Logic verification of superconducting electronic circuits, including for margin analysis of yield

A method comprising:

• for a plurality of different operating conditions of a superconducting electronic circuit for implementing a desired logic function, the superconducting electronic circuit having a plurality of nodes:
• simulating operation of the superconducting electronic circuit at the operating condition, including probing signal values of the nodes;
• deriving phase state transitions from the signal values;
• and
• verifying, based on the phase state transitions, whether the superconducting electronic circuit implements the desired logic function under the operating condition;
• and
• estimating a yield of the superconducting electronic circuit based on the logic verifications performed for the plurality of different operating conditions.

A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to:

• in a simulation of a superconducting electronic circuit having a plurality of nodes, probe signal values of the nodes;
• derive phase state transitions from the signal values;
• and
• verify, based on the phase state transitions, whether the superconducting electronic circuit implements the desired logic function;
• wherein the simulation of the superconducting electronic circuit runs over a sufficient number of sequential cycles to account for hysteresis effects in the superconducting electronic circuit.