Back to results
US 12,608,470 B2Granted
Cyberattack countermeasure circuits and methods
AssigneeMicrosoft Technology Licensing, LLC
InventorsKunyan Liu, Yucong Tao
Life of this patent
Estimating the term…
Abstract
Embodiments of the present disclosure include countermeasure circuit techniques for cyberattacks. In one embodiment, portions of combinational logic receive shared input bit groups and produce shared output bit groups. Shared output bit groups may be coupled between series configured combinational logic portions using control gates. Clock signals are delayed to activate the control gates after the outputs are stable. In some embodiments, a first combinational logic group and second combinational logic group operate on a clock and inverse clock.
Claims20
A circuit comprising:
- a plurality of combinational logic circuit groups each comprising a plurality of combinational logic circuits configured in series, wherein each combinational logic circuit comprises a plurality of combinational logic circuit portions, and each combinational logic circuit portion receives one or more of a plurality of shared input bit groups and produces a shared output bit group;
- a plurality of registers configured between the plurality of combinational logic circuit groups, each register having a control input;
- a plurality of control gate circuits configured between the plurality of combinational logic circuit portions of the plurality of combinational logic circuit groups;
- and
- a plurality of delay circuits, each delay circuit configured between the control input of a particular register and a control input of a control gate circuit, wherein a plurality of shared output bit groups of upstream combinational logic circuits form the plurality of shared input bit groups of downstream combinational logic circuits, and wherein each combinational logic circuit portion of a particular downstream combinational logic circuit receives less than a total of the plurality of shared input bit groups.
2 more elements
A method of preventing cyberattacks comprising:
- receiving a plurality of shared input bit groups in a plurality of combinational logic circuit portions of a plurality of combinational logic circuit groups, each combinational logic circuit group comprising a plurality of combinational logic circuits configured in series, wherein each combinational logic circuit comprises the plurality of combinational logic circuit portions;
- receiving a clock signal in a plurality of registers configured between the plurality of combinational logic circuit groups, each register having a control input to receive the clock signal;
- delaying the clock signal to produce a plurality of delayed clock signals;
- receiving the plurality of delayed clock signals in a plurality of control gate circuits configured between the plurality of combinational logic circuits of the plurality of combinational logic circuit groups;
- and
- producing, by each combinational logic circuit portion, a shared output bit group, wherein shared output bit groups of upstream combinational logic circuits form shared input bit groups of downstream combinational logic circuits, and wherein each combinational logic circuit portion of a particular downstream combinational logic circuit receives less than a total of the plurality of shared output bit groups of a particular upstream combinational logic circuit.
3 more elements
A circuit comprising:
- a first register that receives a clock signal;
- a first combinational logic circuit group comprising a first plurality of combinational logic circuits configured in series;
- a second register;
- a second combinational logic circuit group comprising a second plurality of combinational logic circuits configured in series, wherein each combinational logic circuit comprises a plurality of combinational logic circuit portions, and each combinational logic circuit portion receives one or more of a plurality of shared input bit groups and produces a shared output bit group, wherein each combinational logic circuit portion of a particular downstream combinational logic circuit receives less than a total of the plurality of shared input bit groups;
- a plurality of multiplexers configured between the plurality of combinational logic circuit portions, each multiplexer having one input coupled to ground;
- a first delay circuit configured between a control input of the first register and a control input of a first portion of the multiplexers;
- and
- a second delay circuit configured between a control input of the second register and a control input of a second portion of the multiplexers, wherein a plurality of shared output bit groups of upstream combinational logic circuits form the shared input bit groups of downstream combinational logic circuits, and wherein the downstream combinational logic circuits receive shared input bit groups in response to delayed versions of the clock signal.
5 more elements
Dependencies are inferred from the claim text.