Single instruction multiple dispatches for short kernels in a reconfigurable parallel processor

A processor, comprising:

• a sequencer, including:
• a scalar instruction decoder;
• a scalar processor;
• a vector instruction decoder,
• a local memory, and
• a scalar register file;
• and
• a plurality of columns of vector processing units coupled to the sequencer, wherein the sequencer is configured to:
• retrieve kernel information of a kernel, the kernel information including a number of instances of the kernel to fit in the processor, an address offset, a register index offset, and a number of columns of vector processing units that the kernel occupies;
• retrieve instructions of the kernel from an instruction cache, the instructions of the kernel including a plurality of instruction groups;
• repeatedly execute decoded scalar instructions of each instruction group of the kernel decoded by the scalar instruction decoder successively by the scalar processor according to the number of instances of the kernel, with a first execution of the decoded scalar instructions using addresses in the local memory and scalar registers in the scalar register file specified by the kernel and with each repetition of execution using incremented addresses in the local memory with an increment amount being equal to the address offset multiplied by a respective repetition count and scalar registers with indexes incremented by the register index offset multiplied by the respective repetition count;
• repeatedly decode vector instructions of each instruction group of the kernel successively by the vector instruction decoder according to the number of instances of the kernel, with a first vector instruction decoding using the scalar registers specified by the kernel and with each repetition of decoding using the scalar registers with indexes incremented by the register index offset multiplied by the respective repetition count;
• and
• dispatch a respective configuration to a respective column after the first vector instruction decoding and each repetition of decoding, with each respective configuration being generated after decoding the vector instructions of the instruction group a respective time and being dispatched to a respective column with an amount of space between two subsequent dispatches equal to the number of columns of vector processing units that the kernel occupies.