Page request interface support in handling pointer fetch with caching host memory address translation data

A method comprising:

• buffering, in a pointer buffer of host interface circuitry of a processing device, a plurality of pointers associated with a plurality of chop commands of a logical block address (LBA) read command residing in a submission queue of a host system;
• sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit comprising a subset of the plurality of pointers;
• detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command of the plurality of chop commands;
• and
• sending a translation miss message to a page request interface (PRI) handler, the translation miss message containing a restart point, for the chop command, comprising a logical block address at one of a beginning of the chop command or at the translation unit within the pointer buffer;
• sending, by the PRI handler, a page miss request to a translation agent of the host system;
• receiving, by the PRI handler, a page miss response from the translation agent;
• and
• responsive to the page miss response, causing to be inserted, by the PRI handler in the pointer buffer, ones of the plurality of pointers corresponding to chop commands starting from the restart point of the pointer buffer identified by the page miss response.

A non-transitory computer-readable medium storing instructions, which when executed by a processing device of a memory sub-system, causes the processing device to perform operations comprising:

• buffering, in a pointer buffer of host interface circuitry of a processing device, a plurality of pointers associated with a plurality of chop commands of a logical block address (LBA) read command residing in a submission queue of a host system;
• sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit comprising a subset of the plurality of pointers;
• detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command of the plurality of chop commands;
• and
• sending a translation miss message to a page request interface (PRI) handler, the translation miss message containing a restart point, for the chop command, comprising a logical block address at one of a beginning of the chop command or at the translation unit within the pointer buffer;
• sending, by the PRI handler, a page miss request to a translation agent of the host system;
• receiving, by the PRI handler, a page miss response from the translation agent;
• and
• responsive to the page miss response, causing to be inserted, by the PRI handler in the pointer buffer, ones of the plurality of pointers corresponding to chop commands starting from the restart point of the pointer buffer identified by the page miss response.