Computing core, accelerator, computing method and apparatus, device, non-volatile readable storage medium, and system

A computing method, comprising:

• generating a computing instruction for each matrix multiplication operation in a graph neural network, and wherein a parallel count N and a write location of a matrix multiplication result of the corresponding matrix multiplication operation are set in the computing instruction;
• and
• sending the computing instruction to an accelerator, so that the accelerator performs accelerated computing on the graph neural network, and wherein the accelerator comprises a controller, a first memory, a second memory whose transmission bandwidth is greater than that of the first memory, and a computing core;
• and
• the controller is respectively connected to the first memory, the second memory, and the computing core, and the computing core is respectively connected to the first memory and the second memory;
• the controller is configured to send a computing instruction for a matrix multiplication operation in a graph neural network to the first memory, the second memory, and the computing core;
• the first memory is configured to obtain and store, in a direct memory access (DMA) mode according to the computing instruction, a first matrix participating in a current matrix multiplication operation;
• the second memory is configured to obtain and store, in the DMA mode according to the computing instruction, a second matrix participating in the current matrix multiplication operation;
• and
• the computing core is configured to compute a matrix multiplication result of the first matrix and the second matrix according to the computing instruction, and wherein
• the computing core comprises a first cache component, a second cache component, a matrix multiplication computing component, and an output component;
• and
• the first cache component is configured to load data in a first matrix participating in a current matrix multiplication operation in a graph neural network from an external first memory according to a received computing instruction;
• the second cache component is configured to load data in a second matrix participating in the current matrix multiplication operation from an external second memory according to the computing instruction;
• the matrix multiplication computing component, configured to compute matrix multiplication results of N pieces of row data or N pieces of column data in the first matrix and N pieces of column data or N pieces of row data in the second matrix in parallel based on a parallel count N set in the computing instruction;
• and
• the output component is configured to temporarily store the matrix multiplication results, and write, in response to a data volume of the matrix multiplication results satisfying a preset write condition, the matrix multiplication results into the first memory or the second memory set in the computing instruction, and wherein
• a transmission bandwidth of the second memory is greater than that of the first memory;
• and in response to the matrix multiplication results needing to participate in computation in a traversal manner participating in each round of computation in a next matrix multiplication operation, the computing instruction is set with the second memory;
• or in response to the matrix multiplication results having no need to participate in computation in a traversal manner participating in each round of computation in a next matrix multiplication operation, the computing instruction is set with the first memory.

An electronic device, comprising:

• a memory, configured to store a computer program;
• and
• a processor, configured to execute the computer program to implement a computing method;
• and
• the computing method, comprising:
• generating a computing instruction for each matrix multiplication operation in a graph neural network, and wherein a parallel count N and a write location of a matrix multiplication result of the corresponding matrix multiplication operation are set in the computing instruction;
• and
• sending the computing instruction to an accelerator, so that the accelerator performs accelerated computing on the graph neural network;
• and wherein
• the accelerator comprises a controller, a first memory, a second memory whose transmission bandwidth is greater than that of the first memory, and a computing core;
• and
• the controller is respectively connected to the first memory, the second memory, and the computing core, and the computing core is respectively connected to the first memory and the second memory;
• the controller is configured to send a computing instruction for a matrix multiplication operation in a graph neural network to the first memory, the second memory, and the computing core;
• the first memory is configured to obtain and store, in a direct memory access (DMA) mode according to the computing instruction, a first matrix participating in a current matrix multiplication operation;
• the second memory is configured to obtain and store, in the DMA mode according to the computing instruction, a second matrix participating in the current matrix multiplication operation;
• and
• the computing core is configured to compute a matrix multiplication result of the first matrix and the second matrix according to the computing instruction;
• and wherein
• the computing core comprises a first cache component, a second cache component, a matrix multiplication computing component, and an output component;
• and
• the first cache component is configured to load data in a first matrix participating in a current matrix multiplication operation in a graph neural network from an external first memory according to a received computing instruction;
• the second cache component is configured to load data in a second matrix participating in the current matrix multiplication operation from an external second memory according to the computing instruction;
• the matrix multiplication computing component, configured to compute matrix multiplication results of N pieces of row data or N pieces of column data in the first matrix and N pieces of column data or N pieces of row data in the second matrix in parallel based on a parallel count N set in the computing instruction;
• the output component is configured to temporarily store the matrix multiplication results, and write, in response to a data volume of the matrix multiplication results satisfying a preset write condition, the matrix multiplication results into the first memory or the second memory set in the computing instruction, and wherein
• a transmission bandwidth of the second memory is greater than that of the first memory;
• and in response to the matrix multiplication results needing to participate in computation in a traversal manner participating in each round of computation in a next matrix multiplication operation, the computing instruction is set with the second memory;
• or in response to the matrix multiplication results having no need to participate in computation in a traversal manner participating in each round of computation in a next matrix multiplication operation, the computing instruction is set with the first memory.