Sense amplifiers as static random access memory cache

A method, comprising:

• storing first data of a first cache line and first metadata of the first cache line in a row of memory cells of a memory array of a dynamic random access memory (DRAM) device having a plurality of sense amplifiers coupled thereto, wherein first metadata is associated with the first data;
• operating the plurality of sense amplifiers in a first mode in association with sensing second data stored in the array of memory cells;
• and
• operating the plurality of sense amplifiers in a second mode in which the plurality of sense amplifiers serve as a static random access memory (SRAM) cache;
• and
• in the second mode:
• communicating at least a portion of the first data from the plurality of sense amplifiers to a host coupled to the DRAM device;
• and
• receiving, by the plurality of sense amplifiers, third data of a second cache line from the host.

A method, comprising:

• storing first data of a first cache line and first metadata of the first cache line in a row of memory cells of a memory array of a dynamic random access memory (DRAM) device having a plurality of sense amplifiers coupled thereto, wherein first metadata is associated with the first data;
• writing third data and second metadata of a second cache line received from the host to the row of memory cells, wherein the second metadata is associated with the third data;
• and
• storing the first data, the first metadata, the third data, and the second metadata in the row of memory cells concurrently;
• operating the plurality of sense amplifiers in a first mode in association with sensing second data stored in the array of memory cells;
• and
• operating the plurality of sense amplifiers in a second mode in which the plurality of sense amplifiers serve as a static random access memory (SRAM) cache.

A system, comprising:

• a memory device comprising a plurality of banks, each bank comprising a respective memory array coupled to a respective plurality of sense amplifiers;
• and
• a processing device that is on-chip with and coupled to the memory device,
• wherein each respective plurality of sense amplifiers is configured to:
• in a first mode, store a plurality of cache lines, wherein each cache line comprises respective data and respective metadata;
• in the first mode, communicate first data of a first cache line to the processing device;
• in the first mode, store second data of a second cache line received from the processing device;
• and
• in a second mode, sense third data from the memory array, wherein the third data is unassociated with a cache line.