Memory fault tolerance using raid
AssigneeMicron Technology, Inc.
InventorsTony M. Brewer, Craig Warner
Life of this patent
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Abstract
Systems, methods, and computer-readable storage devices can include fabric networks for isolating and correcting failures in the fabric network and device failures. The fabric network connects to a group of devices and a host. The group of devices includes at least a target data device, other data devices, and a parity device. A redundant array of independent devices (RAID) engine, which is coupled to the one group of devices, performs an access operation. The fault tolerant engine is provided in a leaf switch of the fabric network. A routing processor determines a path for a request received from the host to the target data device. The routing processor is coupled to the fault tolerant engine, and the routing processor is provided in the leaf switch.
Claims36
A system comprising:
- at least one group of memory devices including data devices, wherein for a destination address in a memory request, one of the memory devices is a target device and another one of the memory devices is a parity device;
- the at least one group of memory devices and at least one host coupled to a memory switch;
- the memory switch including:
- at least one fault tolerant engine coupled to the at least one group of memory devices configured to perform:
- (i) read access, and (ii) read recovery if one of the memory devices is broken during the read access;
- or
- (i) write access including updating data of the target device and parity data of the parity device atomically and (ii) write recovery if one of the memory devices is broken during the write access;
- at least one routing processor (i) coupled to the memory switch and (ii) configured to determine a path for the memory request received from the at least one host to the target device and directing the memory request to the target device;
- wherein when one of the memory devices is broken during the write access, the fault tolerant engine is configured to execute an atomic write access by:
- (i) locking an entire parity group of lines containing the target device to prevent a subsequent write access request to the target device from accessing the target device while the fault tolerant engine is writing to the target device;
- and
- (ii) unlocking the entire parity group of lines when the write access is complete so that the subsequent write access request can be performed;
- wherein the fault tolerant engine is configured to generate new data by performing the atomic write access and a partial cache line write operation;
- and
- wherein the partial cache line write operation prevents a portion of existing data from being overwritten by the new data when the new data is written to the target device.
A non-transitory computer readable medium having stored thereon computer executable instructions that, if executed by a computing device, cause the computing device to perform a method for use by a memory controller of a memory system including:
- at least one group of memory devices;
- wherein for a destination address in a memory request, one of the devices is a target device and another one of the devices is a parity device;
- at least one fabric (i) coupled to the at least one group of memory devices and at least one host and (ii) comprising:
- a memory switch including at least one fault tolerant engine coupled to each of the memory devices in the at least one group, the method comprising:
- performing (i) read access, and (ii) read recovery if one of the memory devices is broken during the read access;
- or
- performing (i) write access including updating data of the target device and parity data of the parity device atomically and (ii) write recovery if one of the memory devices is broken during the write access;
- wherein at least one routing processor coupled to the memory switch is configured to determine a path for the memory request received from the at least one host to the target device and directing the memory request to the target device;
- wherein when one of the memory devices is broken during the write access, the fault tolerant engine is configured to execute an atomic write access operation by:
- (i) locking an entire parity group of lines containing the target device to prevent a subsequent write access request to the target device from accessing the target device while the fault tolerant engine is writing to the target device;
- and
- (ii) unlocking the entire parity group of lines when the write access is complete so that the subsequent write access request can be performed;
- wherein the fault tolerant engine is configured to generate new data by performing the atomic write access operation and a partial cache line write operation;
- and
- wherein the partial cache line write operation prevents a portion of existing data from being overwritten by the new data when the new data is written to the target device.
A method utilizing one or more processors and one or more memories, the method comprising:
- providing at least one group of memory devices;
- wherein, for a destination address in a memory request, one of the devices is a target device and another one of the devices is a parity device;
- and
- providing at least one fabric (i) coupled to the at least one group of memory devices and at least one host and (ii) comprising a memory switch including at least one fault tolerant engine coupled to each of the memory devices in the at least one group or memory devices configured to perform:
- (i) a read access, and (ii) read recovery if one of the memory devices is broken during the read access;
- or
- (i) write access including updating data of the target device and parity data of the parity device atomically and (ii) write recovery if one of the memory devices is broken during the write access;
- providing at least one routing processor (i) coupled to the memory switch and (ii) configured to determine a path for the memory request received from the at least one host to the target device and directing the memory request to the target device;
- wherein when one of the memory devices is broken during the write access, the fault tolerant engine is configured to execute an atomic write access operation by:
- (i) locking an entire parity group of lines containing the target device to prevent a subsequent write access request to the target device from accessing the target device while the fault tolerant engine is writing to the target device;
- and
- (ii) unlocking the entire parity group of lines when the write access is complete so that the subsequent write access request can be performed;
- wherein the fault tolerant engine is configured to generate new data by performing the atomic write access operation and a partial cache line write operation;
- and
- wherein the partial cache line write operation prevents a portion of existing data from being overwritten by the new data when the new data is written to the target device.
Dependencies are inferred from the claim text.