Crash handling in a heterogeneous computing platform
AssigneeDell Products L.P.
InventorsIbrahim Sayyed, Adolfo S. Montero, Alan H. Abdelhalim
Life of this patent
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Abstract
Systems and methods include an Information Handling System (IHS) that is adapted to provide crash handling that is particularized to each phase of the IHS boot sequence. A boot sequence is initiated that includes two or more phases. Prior to each phase of the boot sequence, a crash handler is initiated that is configured to collect state information for IHS hardware configured during that respective phase of the boot sequence. Upon detecting a boot sequence crash by the IHS, the crash handler operating during the phase of the boot sequence of the crash stores hardware state information it has collected to a shared memory location.
Claims20
An Information Handling System (IHS), comprising:
- an NVRAM (Non-Volatile Random-Access Memory) storing boot instructions;
- and
- one or more processors coupled to the NVRAM, wherein execution of the boot instructions by the processors causes the IHS to:
- initiate a boot sequence that includes two or more phases;
- prior to each phase of the boot sequence, initiate a crash handler configured to collect state information for IHS hardware configured during a respective phase of the boot sequence;
- and
- upon detecting a crash by the IHS occurring during one phase of the boot sequence, store hardware state information and information identifying the one phase of the boot sequence corresponding to the occurrence of the crash collected by an operative crash handler to a shared memory location.
A method for crash handling by an Information Handling System (IHS), the method comprising:
- initiating a boot sequence that includes two or more phases;
- prior to each phase of the boot sequence, initiating a crash handler configured to collect state information for IHS hardware configured during a respective phase of the boot sequence;
- and
- upon detecting a crash by the IHS occurring during one phase of the boot sequence, storing hardware state information and information identifying the one phase of the boot sequence corresponding to the occurrence of the crash collected by an operative crash handler to a shared memory location.
An NVRAM (Non-Volatile Random-Access Memory) storage device having instructions stored thereon, wherein execution of the instructions by one or more processors of an IHS (Information Handling System) causes the processor to:
- initiate a boot sequence that includes two or more phases;
- prior to each phase of the boot sequence, initiate a crash handler configured to collect state information for IHS hardware configured during a respective phase of the boot sequence;
- and
- upon detecting a crash by the IHS occurring during one phase of the boot sequence, store hardware state information and information identifying the one phase of the boot sequence corresponding to the occurrence of the crash collected by an operative crash handler to a shared memory location.
Dependencies are inferred from the claim text.