Scrubbing of fault-tolerant digital register storage memory

A memory device comprising:

• a data input port configured to receive input data, the input data representing a bit of data in a first state or a second state;
• a fault-tolerant digital register circuit configured to store state data representing a bit of data in the first state or the second state;
• a data output port configured to produce output data, the output data representing the state data stored in the fault-tolerant digital register circuit;
• a multiplexer operatively coupled to the data input port and the data output port, the multiplexer configured to select, based on a functional enable signal, one of the data input port and the data output port to pass to the fault-tolerant data register circuit;
• and
• a clock gate circuit operatively coupled to a source clock input and a clock input of the fault-tolerant digital register circuit, the clock gate circuit configured to gate the clock input to the fault-tolerant digital register circuit based at least in part on a scrub enable signal;
• wherein the fault-tolerant digital register circuit includes a voter configured to generate output data at the data output port, the output data representing which of the first state and the second state are in a majority among the state data stored in the fault-tolerant digital register circuit.

A method of scrubbing a memory device, the memory device comprising at least a triply redundant digital register circuit configured to store state data representing a bit of data in a first state or a second state, the method comprising:

• waiting for a functional enable signal to not be asserted;
• waiting for a counter or a timer to expire, the counter or the timer incremented by a clock;
• and
• asserting, responsive to the counter or the timer being expired, a scrub enable signal to the triply redundant digital register circuit,
• wherein the triply redundant digital register circuit comprises at least three digital storage circuits arranged in parallel, the at least three digital storage circuits each configured to the store state data;
• and a multiplexer configured to select, based on a functional enable signal, one of a data input port and a data output port to pass into the triply redundant data register circuit.