Processor selectively executing first instruction using non-pre-processed data or second instruction using pre-processed data

A processor comprising:

• an instruction decoder;
• an operation executor configured to execute pipeline processing of an operation instruction, wherein the operation executor includes
• a first register configured to hold data to be used for an operation,
• a pre-processor configured to pre-process the data held in the first register,
• a second register configured to hold the data pre-processed by the pre-processor,
• an operator configured to execute the operation on the data held in the first register or the data held in the second register, and
• a selector configured to connect an output of the first register or an output of the second register to an input of the operator, and
• wherein the instruction decoder generates control information that causes the data held in the first register to be output from the pre-processor without pre-processing the data held in the first register;
• a plurality of pre-processing stages connected in series between the first register and the selector, the plurality of pre-processing stages each including the pre-processor and the second register, wherein the instruction decoder is configured to decode a first operation instruction and a plurality of types of second operation instructions, the first operation instruction causing the operator to execute a first operation on the data held in the first register without allowing the pre-processor to pre-process the data held in the first register, each of the plurality of types of the second operation instructions causing the pre-processor to pre-process the data held in the first register and then causing the operator to execute a second operation on the pre-processed data, and a number of the plurality of types of the second operation instructions corresponding to a number of the pre-processing stages that pre-process data;
• and
• a selection signal generator configured to generate a selection signal that causes the selector to select an output of the second register, the second register being configured to hold the data pre-processed by one of the second operation instructions, in a cycle in which the operator executes the second operation on the data pre-processed according to one or more of the plurality of types of the second operation instructions, and in a cycle in which the operator executes the first operation according to the first operation instruction when the first operation instruction following one of the plurality of types of the second operation instructions is supplied to the operation executor, wherein the instruction decoder generates control information that causes data input to the pre-processor in a corresponding one of the plurality of the pre-processing stages to be output from the corresponding one of the pre-processors without pre-processing the data, based on a decoded result of the first operation instruction.