US 12,608,202 B2Granted

Floating-point scalar comparison with enhanced flags

AssigneeIntel Corporation

InventorsJohn Morgan, Deepti Aggarwal, Michael Espig, H. Peter Anvin

Life of this patent

Estimating the term…

Abstract

Detailed herein are examples of instructions and their hardware support for floating-point comparison that makes use of the distinction between signed integer comparison and unsigned integer comparison to make an analogous distinction between floating-point relationships including unordered and those that do not. These instructions may reduce the number of instructions required to compare and conditionally execute operations in a program, including instructions to load values and instructions to explicitly test for the unordered condition.

Claims20

Dependent claims

An apparatus comprising:

decoder circuitry to decode an instance of single instruction, the single instruction to include at least having one or more fields for an opcode and location information for a first source and a second source, wherein the opcode is to indicate execution circuitry is to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register at least having an overflow flag (OF), a parity flag (PF), a sign flag (SF), a carry flag (CF), and a zero flag (ZF) according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1;
and
execution circuitry to execute the decoded single instruction according to the opcode to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1.

8 more elements

A system comprising:

memory to store an instance of a single instruction;
decoder circuitry to decode the instance of the single instruction, the single instruction to include at least having one or more fields for an opcode and location information for a first source and a second source, wherein the opcode is to indicate execution circuitry is to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register at least having an overflow flag (OF), a parity flag (PF), a sign flag (SF), a carry flag (CF), and a zero flag (ZF) according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1;
and
execution circuitry to execute the decoded single instruction according to the opcode to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1.

9 more elements

A method comprising:

decoding an instance of single instruction, the single instruction to include at least having one or more fields for an opcode and location information for a first source and a second source, wherein the opcode is to indicate execution circuitry is to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register at least having an overflow flag (OF), a parity flag (PF), a sign flag (SF), a carry flag (CF), and a zero flag (ZF) according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1;
and
executing, using execution circuitry, the decoded single instruction according to the opcode to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/217,543Filed 1 Jul 2023 · us provisional application
Priority: 26 Sep 2022
Published: US 2024/0103866 A128 Mar 2024
Granted: 21 Apr 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 7/02
Methods or arrangements for processing data by operating upon the order or content of the data handled: comparing digital values
G06F 9/30021
To perform operations on data operands: compare instructions, e.g. Greater-Than, Equal-To, MINMAX
G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations
G06F
Computing and data processing

Family

Application63/410,100Us provisional application · filed 26 Sep 2022
US 2024/0103866 A1Pre-grant publication · published 28 Mar 2024
US 12,608,202 B2This patent

From the US filing history. Foreign family members aren’t listed.

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Abstract

An apparatus comprising:

decoder circuitry to decode an instance of single instruction, the single instruction to include at least having one or more fields for an opcode and location information for a first source and a second source, wherein the opcode is to indicate execution circuitry is to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register at least having an overflow flag (OF), a parity flag (PF), a sign flag (SF), a carry flag (CF), and a zero flag (ZF) according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1;
and
execution circuitry to execute the decoded single instruction according to the opcode to perform an unordered compare of at least one floating-point value of the each of the two source operands and stores a result of the comparison in a flags register according to the following:
when the floating-point value of the first source is greater than the floating-point value of the second source set OF=0, SF=0, ZF=0, PF=0, and CF=0,
when the floating-point value of the first source is equal to the floating-point value of the second source set OF=1, SF=1, ZF=1, PF=0, and CF=0,
when the floating-point value of the first source is less than the floating-point value of the second source set OF=1, SF=0, ZF=0, PF=0, and CF=1, and
when the floating-point value of the first source is unordered with the floating-point value of the second source set OF=1, SF=1, ZF=0, PF=1, and CF=1.

8 more elements

Facts

Application

18/217,543Filed 1 Jul 2023 · us provisional application

Priority

26 Sep 2022

Published

US 2024/0103866 A128 Mar 2024

Granted

21 Apr 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 7/02
Methods or arrangements for processing data by operating upon the order or content of the data handled: comparing digital values
G06F 9/30021
To perform operations on data operands: compare instructions, e.g. Greater-Than, Equal-To, MINMAX
G06F 9/30036
To perform operations on data operands: instructions to perform operations on packed data, e.g. vector, tile or matrix operations
G06F
Computing and data processing