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US 12,608,199 B2Granted
Instruction set architecture support for a load global pointer instruction
AssigneeIntel Corporation
InventorsDavid B. Sheffield, Erich Boleyn, Jonathan Pearce, Sofia Pediaditaki, Jeffrey Cook, Shreesha Srinath, Ching-Kai Liang, Tyler Sondag
Life of this patent
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Abstract
Techniques for synchronous microthreaded execution are described. An example includes a logical processor to execute one or more threads in a first mode; and a synchronous microthreading (SyMT) co-processor coupled to the logical processor to execute lightweight microthreads, with each lightweight microthread having an independent register state, upon an execution of an instruction to enter into SyMT mode.
Claims24
An apparatus comprising:
- decoder circuitry to decode an instance of a single instruction, the single instruction to include an opcode to indicate that execution circuitry is to load a global pointer from memory, wherein the global pointer is to be used to pass state from a host thread to one or more microthreads, wherein each microthread of the one or more microthreads has its own state;
- and
- execution circuitry to execute the decoded instruction to load the global pointer from memory only when a mode of operation is synchronous microthreading.
A system comprising:
- memory to store an instance of a single instruction;
- and
- an apparatus comprising:
- decoder circuitry to decode an instance of a single instruction, the single instruction to include an opcode to indicate that execution circuitry is to load a global pointer from memory, wherein the global pointer is to be used to pass state from a host thread to one or more microthreads, wherein each microthread of the one or more microthreads has its own state;
- and
- execution circuitry to execute the decoded instruction to load the global pointer from memory only when a mode of operation is synchronous microthreading.
3 more elements
A method comprising:
- translating an instance of a single instruction of a first instruction set to one or more instructions of a second instruction set, the single instruction to include a field for an opcode to indicate that execution circuitry is to load a global pointer from memory, wherein the global pointer is to be used to pass state from a host thread to one or more microthreads, wherein each microthread of the one or more microthreads has its own state;
- decoding the one or more instructions of the second instruction set;
- and
- executing the decoded instruction according to the opcode to load a global pointer from memory only when a mode of operation is synchronous microthreading.
1 more element
Dependencies are inferred from the claim text.