Techniques to reduce power consumption for a distributed computational model mapped onto a multi-processing node system

A method comprising:

• maintaining, at gate clock circuitry, a memory cache arranged to include an indicator of availability of data to be processed by compute circuitry of a first processing node;
• detecting that a second processing node has written one or more blocks of data to a buffer local to the first processing node;
• updating the indicator to indicate a number of blocks of data that was detected as written to the buffer;
• and
• gating a clock signal to the compute circuitry to cause the compute circuitry to stall responsive to the updated indicator indicating an insufficient number of blocks of data was detected for the compute circuitry to process in an execution cycle.

At least one non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed by gate clock circuitry of a processing node, cause the gate clock circuitry to:

• maintain a memory cache arranged to include an indicator of availability of data to be processed by compute circuitry of the processing node;
• detect that another processing node has written one or more blocks of data to a buffer local to the processing node;
• update the indicator to indicate a number of blocks of data that was detected as written to the buffer;
• and
• responsive to the updated indicator indicating an insufficient number of blocks of data was detected for the compute circuitry to process in an execution cycle, gate a clock signal to the compute circuitry to cause the compute circuitry to stall.

A system comprising:

• a first processing node to receive blocks of data to be consumed by a first compute circuitry at the first processing node in an execution cycle;
• and
• a second processing node to write one or more blocks of data to a buffer local to the first processing node, the buffer to have a capacity of N blocks of data, wherein the second processing node includes gate clock circuitry to:
• maintain a memory cache arranged to include an indicator of available capacity of the buffer to receive one or more data blocks produced by a second compute circuitry at the second processing node;
• responsive to detecting that the first processing node has consumed one or blocks of data previously written to the buffer by the second processing node, update the indicator to indicate a number of blocks of data that was detected as consumed;
• and
• responsive to the updated indicator indicating an insufficient available capacity of the buffer to receive data produced by the second compute circuitry, gate a clock signal to the compute circuitry to cause the second compute circuitry to stall.