Flash memory scheme capable of controlling flash memory device automatically generating debug information and transmitting debug information back to flash memory controller with making memory cell array generating errors

A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, and the method comprises:

• providing an input/output (I/O) control circuit, coupled to the flash memory controller through the specific communication interface;
• providing a command register, coupled to the I/O control circuit, for buffering command information sent from the flash memory controller and transmitted through the I/O control circuit;
• providing an address register, coupled to the I/O control circuit, for buffering address information sent from the flash memory controller and transmitted through the I/O control circuit;
• providing a memory cell array, at least having a first plane and a second plane which is different from the first plane;
• providing at least one address decoder, coupled to the memory cell array;
• providing a status register, coupled to the I/O control circuit;
• providing a voltage generator, coupled to the memory cell array;
• using a debug circuit to automatically generate debug information of an access operation of an access command signal sent from the flash memory controller with actually controlling the voltage generator making the memory cell array generate failure errors;
• and
• transmitting the generated debug information into the status register and controlling the status register transmitting the debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface;
• wherein the access operation is a program operation, a cache program operation, or an erase operation;
• the debug information is associated with a true program failure, a true cache program failure, or a true erase failure, and the debug circuit controls the memory cell array generating a program failure error, a cache program failure error, or an erase failure error;
• the step of using the debug circuit comprises:
• using the debug circuit to configure an operation of the debug circuit associated with an error handle debug mode according to content carried in an error injection set-feature signal sent from the flash memory controller to the flash memory device;
• and
• determining whether to enter the error handle debug mode in response to a reception of the access command signal and then to automatically generate the debug information of the access operation in the error handle debug mode.

A flash memory controller to be used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface, comprising:

• an input/output (I/O) circuit, coupled to the flash memory device through the specific communication interface, for sending commands and data between the flash memory device and a processor;
• and
• the processor, coupled to the I/O circuit, for controlling the I/O circuit sending an error injection set-feature signal to the flash memory device through the specific communication interface to configure an operation of a debug circuit of the flash memory device according to content carried in an error injection set-feature signal sent from the flash memory controller to the flash memory device to make the debug circuit determine whether to enter an error handle debug mode in response to a reception of an access command signal and then to automatically generate debug information of an access operation of the access command signal sent from the flash memory controller in the error handle debug mode, transmit the generated debug information from the flash memory device to the flash memory controller via the I/O control circuit and the specific communication interface, with actually controlling a memory cell array of flash memory device generating failure errors;
• wherein the access operation is a program operation, a cache program operation, or an erase operation;
• the debug information is associated with a true program failure, a true cache program failure, or a true erase failure, and the debug circuit controls the memory cell array generating a program failure error, a cache program failure error, or an erase failure error.