Direct digital synthesizer circuit, measurement system, and method of operating a direct digital synthesizer circuit

A method of operating a direct digital synthesizer (DDS) circuit by a measurement system, the measurement system comprising the direct digital synthesizer (DDS) circuit, at least one additional direct digital synthesizer (DDS) circuit, and an analysis circuit, wherein the direct digital synthesizer (DDS) circuit comprises a phase accumulator circuit having a clock input configured to receive a clock signal, a frequency tuning register configured to receive a frequency tuning word, a phase shift register configured to receive a phase shift word, a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal or based on the frequency tuning word, a feedback path configured to feed back the phase signal to the phase increment sub-circuit, and a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word,

• the method comprising:
• generating, by the direct digital synthesizer (DDS) circuit, an analog output signal;
• generating, by the at least one additional direct digital synthesizer (DDS) circuit, an additional analog output signal;
• receiving, by the analysis circuit, the analog output signal of the direct digital synthesizer (DDS);
• receiving, by the analysis circuit, the additional analog output signal of the additional direct digital synthesizer (DDS) as a phase reference signal;
• determining, by the analysis circuit, a phase shift word based on the analog output signal and based on the phase reference signal;
• and
• adapting, by the phase correction sub-circuit of the direct digital synthesizer (DDS) circuit, the phase signal output by the phase accumulator circuit based on the phase shift word.

A measurement system, comprising:

• a first direct digital synthesizer circuit configured to generate a first analog output signal, the first direct digital synthesizer circuit comprising a phase accumulator circuit, the phase accumulator circuit comprising:
• a clock input configured to receive a clock signal;
• a frequency tuning register configured to receive a frequency tuning word;
• a phase shift register configured to receive a phase shift word;
• a phase increment sub-circuit configured to increment a phase signal output by the phase accumulator circuit by a predetermined phase increment based on the clock signal or on the frequency tuning word;
• a feedback path being configured to feed back the phase signal to the phase increment sub-circuit;
• and
• a phase correction sub-circuit configured to adapt the phase signal fed back to the phase increment sub-circuit based on the phase shift word;
• a second direct digital synthesizer circuit configured to generate a second analog output signal;
• and
• an analysis circuit configured to:
• receive the first analog output signal of the first direct digital synthesizer circuit;
• receive the second analog output signal of the second direct digital synthesizer circuit, the second analog output signal being a phase reference signal, and
• determine the phase shift word based on the first analog output signal of the first direct digital synthesizer circuit and based on the second analog output signal of the second direct digital synthesizer circuit.