Power management device and electronic device including the same

An electronic device comprising:

• a main processor including a plurality of first power domains;
• and
• a power management device configured to generate a plurality of output voltages in association with a power sequence of the plurality of first power domains, and provide the plurality of output voltages to the plurality of first power domains through voltage rails,
• wherein the power management device includes:
• a main power management integrated circuit (PMIC) configured to communicate with the main processor through a system bus;
• and
• at least one sub PMIC configured to communicate with the main PMIC through a dedicated pin, wherein the main PMIC includes a first pin and is configured to:
• enable first functions associated with a first initial operation during a stand-by period before generating first output voltages based on a battery voltage;
• and
• apply a first sub enable signal to the at least one sub PMIC through the first pin based on a power-on signal after completing the first initial operation, and
• wherein the at least one sub PMIC includes a second pin and is configured to:
• receive the first sub enable signal through the second pin;
• and
• enable second functions associated with a second initial operation based on the battery voltage, in response to an activation of the first sub enable signal.

A power management device comprising:

• a main power management integrated circuit (PMIC);
• and
• at least one sub PMIC configured to communicate with the main PMIC through a dedicated pin,
• wherein the main PMIC includes a first pin and is configured to:
• enable first functions associated with a first initial operation during a stand-by period before generating first output voltages based on a battery voltage;
• and
• apply a sub enable signal to the at least one sub PMIC through the first pin based on a power-on signal after completing the first initial operation,
• wherein the at least one sub PMIC includes a second pin and is configured to:
• receive the sub enable signal through the second pin;
• and
• enable second functions associated with a second initial operation based on the battery voltage, in response to an activation of the sub enable signal,
• wherein the main PMIC is configured to:
• generate a reference voltage based on the battery voltage in response to the battery voltage reaching a reference level;
• activate the sub enable signal in response to the reference voltage reaching a target level and an activation of the power-on signal;
• and
• apply the sub enable signal to the at least one sub PMIC through the first pin.