Shared non-blocking crossbar buffer circuits and methods
AssigneeAltera Corporation
InventorsSreedhar Ravipalli, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu
Life of this patent
Estimating the term…
Abstract
A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.
Claims20
A circuit system comprising:
- a processing circuit;
- an accelerator circuit;
- and
- a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit, wherein the buffer circuit functions as a crossbar circuit by allowing the accelerator circuit and the processing circuit to access first ones of the packets of data stored in the buffer circuit during access to a second one of the packets of data stored in the buffer circuit, wherein the buffer circuit allows the accelerator circuit and the processing circuit to access a third one of the packets of data stored in the buffer circuit at different times without blocking.
A method for accessing buffer circuit in a circuit system, the method comprising:
- accessing at least a portion of a first packet of data stored in the buffer circuit during a first data access using a processing circuit in the circuit system;
- performing a first function with the processing circuit using the portion of the first packet of data accessed from the buffer circuit;
- accessing at least a portion of a second packet of data stored in the buffer circuit during a second data access using an accelerator circuit in the circuit system concurrently with the first data access;
- performing a second function with the accelerator circuit using the portion of the second packet of data accessed from the buffer circuit;
- and
- allowing the accelerator circuit and the processing circuit to access a third packet of data stored in the buffer circuit at different times without blocking.
A circuit system comprising:
- programmable logic circuits;
- and
- a crossbar buffer circuit, wherein a first one of the programmable logic circuits is configurable to access at least a portion of a first packet of data stored in the crossbar buffer circuit during a first data access, wherein a second one of the programmable logic circuits is configurable to access at least a portion of a second packet of data stored in the crossbar buffer circuit during a second data access concurrently with the first data access,
- wherein the crossbar buffer circuit allows the first one of the programmable logic circuits to access only the portion of the first packet of data stored in the crossbar buffer circuit, and wherein the crossbar buffer circuit allows the second one of the programmable logic circuits to access only the portion of the second packet of data stored in the crossbar buffer circuit.
Dependencies are inferred from the claim text.