Random transient power test signal generator based on three-dimensional memristive discrete map

A random transient power test signal generator based on three-dimensional memristive discrete map, comprising:

• a timing control module implemented by a field programmable gate array, which is used for counting a system clock, wherein when the counting value of the timing control module reaches a counting threshold DM_CNT, the output of the timing control module as a system enable signal Ensys turns into high level and holds on a system clock cycle, and then turns into low level, the period of system enable signal Ensys is the updating period of a random transient power testing signal, which is denoted by t1;
• a three-dimensional parallel bi-memristor Logistic map module implemented by the field programmable gate array, which is used for generating two pseudo-random sequences, the mapping model of the three-dimensional parallel bi-memristor Logistic map is:
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• where a is a parameter of logistic mapping, b and c respectively are coupling coefficients between discrete memristors
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• and the logistic mapping, k0, k1, k2 respectively are the 0-order coefficient, the 1-order coefficient and the 2-order coefficient of discrete memristor
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• respectively are the three-dimensional status values of time n, xn+1, yn+1 and zn+1 respectively are the three-dimensional status values of time n+1;
• when a rising edge occurs in system enable signal Ensys, starting the three-dimensional parallel bi-memristor Logistic map module to update the three-dimensional status values according to the mapping model and inputted three-dimensional initial status values x0, y0, z0;
• after time duration of t2, ending the update, the time of ending is denoted by L, then taking P three-dimensional status values xL, xL-1, . . . , XL-P+1 as one pseudo-random sequence, which is denoted by x[P−1:0], and taking P three-dimensional status values yL, yL-1, . . . , yL-P+1 as another pseudo-random sequence, which is denoted by y[P−1:0];
• meanwhile, when starting the three-dimensional parallel bi-memristor Logistic map module to update the three-dimensional status values, an update status signal ENPMLM outputted by the three-dimensional parallel bi-memristor Logistic map module turns into high level and holds on, when the update ends, update status signal ENPMLM automatically is set to 0;
• a waveform output reset module, which is used for generating a waveform output reset signal DDSrst, wherein when a rising edge is detected in system enable signal Ensys, the waveform output reset signal DDSrst is set to low level, when a falling edge is detected in update status signal ENPMLM, the waveform output reset signal DDSrst is set to high level;
• two waveform output modules, one is used for receiving pseudo-random sequence x[P−1:0], another is used for receiving pseudo-random sequence y[P−1:0], waveform output reset signal DDSrst is sent to the two waveform output modules respectively, wherein the waveform output module comprises a DDS (Direct Digital Synthesizer) module, an output control module and an output selection module;
• wherein the DDS module has two registers R1, R2 and a DDS reset module, register R1 is used for storing a frequency control word Kf, M1 bits of status values chosen from the received pseudo-random sequence are taken as a starting phase control word IPh and stored in register R2, waveform output reset signal DDSrst resets the DDS module through the DDS reset module, namely when the level of waveform output reset signal DDSrst is low, the level of a DDS enable signal ENDDS outputted by the DDS reset module is also low, the DDS module doesn't work, when the level of waveform output reset signal DDSrst is high, the level of DDS enable signal ENDDS outputted by the DDS reset module is also high, the DDS module starts to work:
• reading frequency control word Kf from register R1 and generating a M1-bit accumulated address according to the principle of DDS, then adding starting phase control word IPh in register R2 and the M1-bit accumulated address together to obtain a reading address Raddr, then reading waveform data from a waveform memory according to reading address Raddr and taking the waveform data as the output of the DDS module;
• wherein the output control module has a counter reset module, an integral period counter and a decimal period counter, waveform output reset signal DDSrst resets the integral period counter through the counter reset module, namely when the level of waveform output reset signal DDSrst is low, the level of a counter enable signal ENcnt1 outputted by the counter reset module is also low, the integral period counter doesn't work and its counting value CNT1=0, at the same time, a decimal period counter enable signal ENcnt2 outputted by the integral period counter is also low, which makes the level of a DDS selection signal SELDDS outputted by the decimal period counter low;
• wherein the inputs of the integral period counter comprise reading address Raddr obtained in the DDS module, starting phase control word IPh chosen from the received pseudo-random sequence, a control word NP for number of periods and counter enable signal ENcnt1 outputted by the counter reset module, where control word NP for number of periods is composed of the M2 bits of status values chosen from the received pseudo-random sequence;
• when waveform output reset signal DDSrst turns from low level to high level, counter enable signal ENcnt1 outputted by the counter reset module also turns from low level to high level, which enables the integral period counter to work:
• counting value CNT1 of the integral period counter is automatically added by 1 according to the two following rules:
• rule 1:
• if Raddr_dly<Raddr, when Raddr_dly≤Iph and Iph≤Raddr, CNT1=CNT1+1, otherwise, counting value CNT1 remains unchanged;
• rule 2:
• if Raddr_dly>Raddr, when Raddr_dly≤Iph or Iph≤Raddr, CNT1=CNT1+1, otherwise, counting value CNT1 remains unchanged;
• where Raddr_dly is a reading address obtained by delaying reading address Raddr one clock period, namely is the reading address of previous clock period;
• when CNT1=NP, decimal period counter enable signal ENcnt2 outputted by the integral period counter turns into high level, otherwise, remains at low level;
• when CNT1=2M2, DDS enable signal ENDDS is set to low level, which resets the DDS module;
• M3 bits of status values chosen from the received pseudo-random sequence compose an ending phase control word Eph, when decimal period counter enable signal ENcnt2 turns into high level, which enables the decimal period counter, wherein the inputs of the decimal period counter comprise reading address Raddr obtained in the DDS module, ending phase control word Eph chosen from the received pseudo-random sequence and decimal period counter enable signal ENcnt2, DDS selection signal SELDDS outputted by the decimal period counter changes according to the two following rules:
• rule 1:
• if Raddr_dly<Raddr, when Raddr_dly≤Eph and Eph≤Raddr, DDS selection signal SELDDS turns into high level, otherwise, remains at low level;
• rule 2:
• if Raddr_dly>Raddr, when Raddr_dly≤Eph or Eph≤Raddr, DDS selection signal SELDDS turns into high level, otherwise, remains at low level;
• wherein the output selection module is used for selecting the output of the waveform output module according to DDS selection signal SELDDS:
• when the level of DDS selection signal SELDDS is low, selecting the output of the DDS module as the output of the waveform output module, when the level of DDS selection signal SELDDS is high, selecting low level as the output of the waveform output module;
• a two channel Digital to Analog Converter (DAC), each channel configured for respectively performing a digital to analog conversion on the outputs of the two waveform output modules to obtain two signals that are taken as a transient voltage signal and a transient current signal respectively, namely the random transient power testing signal is obtained, the random transient power testing signal constituted of the transient voltage signal and the transient current signal being input to a smart power meter connected to an equipment under test to simulate a dynamic power to the equipment.