Apparatus and methods for voltage droop detection in die architectures

A method by a processor comprising:

• accessing a register of adaptive clock distribution logic configured to increment an event count within the register based on the adaptive clock distribution logic detecting an activation event and the adaptive clock distribution logic changing a frequency of an output clock signal transmitted to safety logic;
• the safety logic supplying one or more functions that support operation of an automobile;
• the adaptive clock distribution logic coupled to the safety logic for protecting the safety logic from irregularities in at least one of clock frequency and voltage;
• reading the event count within the register;
• comparing the event count to a threshold count value;
• and
• based on the comparing of the event count to the threshold count value, transmitting a performance signal to at least one device, the signal indicating performance of the adaptive clock distribution logic.

A non-transitory, machine-readable storage medium comprises instructions that, when executed by at least one processor, cause the at least one processor to:

• access a register of adaptive clock distribution logic configured to increment an event count within the register based on the adaptive clock distribution logic detecting an activation and the adaptive clock distribution logic changing a frequency of an output clock signal transmitted to safety logic;
• the safety logic supplying one or more functions that support operation of an automobile;
• the adaptive clock distribution logic coupled to the safety logic for protecting the safety logic from irregularities in at least one of clock frequency and voltage;
• read the event count within the register;
• compare the event count to a threshold count value;
• and
• based on a result of the comparison of the event count to the threshold value, transmit a performance signal to at least one device, the signal indicating performance of the adaptive clock distribution logic.

An apparatus comprising:

• a memory storing instructions;
• and
• at least one processor communicatively coupled to the memory and being configured to execute the instructions to:
• access a register of adaptive clock distribution logic configured to increment an event count within the register based on the adaptive clock distribution logic detecting an activation event and the adaptive clock distribution logic changing a frequency of an output clock signal transmitted to safety logic;
• the safety logic supplying one or more functions that support operation of an automobile;
• the adaptive clock distribution logic coupled to the safety logic for protecting the safety logic from irregularities in at least one of clock frequency and voltage;
• read the event count within the register;
• compare the event count to a threshold count value;
• and
• based on a result of the comparison of the event count to the threshold value, transmit a status signal to at least one device, the status signal indicating performance of the adaptive clock distribution logic.