Semiconductor chip and semiconductor package including the same

A semiconductor chip comprising:

• a semiconductor substrate;
• an integrated device layer on the semiconductor substrate, wherein integrated devices are in the integrated device layer;
• a multi-wiring layer on the integrated device layer and having at least two layers of wires;
• and
• a pad metal layer on the multi-wiring layer, electrically connected to the wires of the multi-wiring layer, and has test pads therein,
• wherein the pad metal layer extends in a first direction parallel to a top surface of the semiconductor substrate or in a second direction perpendicular to the first direction,
• wherein a test pad of the test pads comprises a central portion of the pad metal layer and is exposed by a protective layer that overlaps the pad metal layer,
• wherein an outer portion of the pad metal layer excluding the test pad overlaps the wires in a third direction perpendicular to the top surface of the semiconductor substrate;
• wherein the multi-wiring layer comprises an isolation region that overlaps the test pad in the third direction,
• wherein the wires are not in the isolation region of the multi-wiring layer;
• wherein bump pads are on a central portion of a top surface of the semiconductor chip, and
• wherein the test pads are on an outer portion of the top surface of the semiconductor chip.