Chamfer-less via integration scheme
AssigneeLam Research Corporation
InventorsSivananda Krishnan Kanakasabapathy, Hui-Jung Wu, Richard Wise, Arpan Pravin Mahorowala
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Abstract
Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.
Claims17
A method comprising:
- providing a substrate having a trench formed in a dielectric material;
- and
- depositing a selectively removable sealant layer conformally in the trench, wherein the selectively removable sealant layer comprises a Group IV metal, the selectively removable sealant layer comprises more than one layer, wherein the selectively removable sealant layer comprises a first layer of tin nitride and a second layer of tin oxide.
An apparatus comprising:
- a process chamber configured to hold a substrate;
- and
- a controller configured to cause the apparatus to:
- receive a substrate having a trench formed in a dielectric material;
- deposit a selectively removable sealant layer conformally in the trench, the selectively removable sealant layer comprises more than one layer, wherein the selectively removable sealant layer comprises a first layer of tin nitride and a second layer of tin oxide;
- form a patterned hard mask on the selectively removable sealant layer;
- etch the dielectric material using the patterned hard mask;
- and
- remove the patterned hard mask and the selectively removable sealant layer to produce a chamferless via.
An apparatus comprising:
- a process chamber configured to hold a semiconductor substrate;
- and
- a controller configured to cause the apparatus to:
- receive a semiconductor substrate comprising a layer of material, a conformal removable sealant layer on the layer of material, and a patterned hard mask on the removable sealant layer, the removable sealant layer comprises more than one layer, wherein the selectively removable sealant layer comprises a first layer of tin nitride and a second layer of tin oxide, the layer of material comprising dielectric material and a metal underlying the dielectric material;
- selectively etch the removable sealant layer relative to the dielectric material to expose the dielectric material;
- etch the dielectric material using the patterned hard mask to expose a surface of the metal;
- and
- remove the patterned hard mask and the removable sealant layer completely to form a via exposing the surface of the metal.
Dependencies are inferred from the claim text.