# US 12,604,785 B2 · Package structure and manufacturing method thereof

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- Number: US 12,604,785 B2
- Document ID: US12604785B2
- Status: Granted
- Kind: B2
- Application number: 18/083,579
- Filed: 2022-12-19
- Published: 2024-01-25
- Granted: 2026-04-14
- Earliest claimed: 2022-07-19
- Assignees: Powertech Technology Inc.
- Applicants: Powertech Technology Inc.
- Inventors: Shang-Yu Chang Chien
- Web page: https://patentgrep.com/patent/US12604785B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 70/69: Insulating materials thereof
- H10W 74/014: {using batch processing}
- H10W 74/017: {Auxiliary layers for moulds, e.g. release layers or layers preventing residue}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/10: characterised by their shape or disposition
- H10W 74/40: characterised by their materials
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer, a conductive pillar, an active chip, an encapsulation layer, and another redistribution layer. The conductive pillar and the active chip are side by side disposed on the redistribution layer. The encapsulation layer surrounds the active chip and the conductive pillar, in which the encapsulation layer has a first through hole disposed between the active chip and the redistribution layer and a second through hole disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole. The another redistribution layer is disposed on a side of the redistribution layer away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar.

## Claims

### Claim 1

A package structure, comprising:
a redistribution layer;
a conductive pillar and an active chip disposed side by side on the redistribution layer, wherein the active chip comprises a pad;
an encapsulation layer surrounding the active chip and the conductive pillar, wherein the encapsulation layer has a first through hole and a second through hole, the first through hole is disposed between the pad of the active chip and the redistribution layer, the second through hole is disposed between the conductive pillar and the redistribution layer, and a depth of the first through hole is less than a depth of the second through hole;
another redistribution layer disposed on a side of the active chip away from the redistribution layer and electrically connected to the redistribution layer through the conductive pillar, wherein a number of dielectric layers of the another redistribution layer is less than a number of dielectric layers of the redistribution layer; and
an anti-warping layer disposed on a side of the another redistribution layer away from the active chip, wherein a thickness of the anti-warping layer is at least twice a thickness of one of the dielectric layers of the another redistribution layer, a Young's modulus of the anti-warping layer is greater than a Young's modulus of polyimide, and the anti-warping layer comprises siloxane polymer, dry film type solder resist material or Ajinomoto laminated film.

### Claim 2 (depends on 1)

The package structure as claimed in claim 1, wherein the redistribution layer comprises a first trace and a second trace, the first trace fills up the first through hole, and the second trace is disposed along a sidewall of the second through hole and a surface of the conductive pillar.

### Claim 3 (depends on 2)

The package structure as claimed in claim 2, wherein the first trace and the second trace are formed of a conductive layer.

### Claim 4 (depends on 3)

The package structure as claimed in claim 3, wherein the conductive layer comprises an interface layer and a metal layer sequentially disposed on the encapsulation layer, and the metal layer is disposed in the first through hole.

### Claim 5 (depends on 3)

The package structure as claimed in claim 3, wherein the first trace contacts the pad.

### Claim 6 (depends on 1)

The package structure as claimed in claim 1, wherein the one of the dielectric layers of the redistribution layer is disposed in the second through hole.

### Claim 7 (depends on 1)

The package structure as claimed in claim 1, wherein the another redistribution layer comprises a conductive layer, the one of the dielectric layers of the another redistribution layer is disposed between the conductive layer and the anti-warping layer, the one of the dielectric layers has a third through hole, the anti-warping layer has a fourth through hole, and the third through hole and the fourth through hole expose the conductive layer.

### Claim 8 (depends on 7)

The package structure as claimed in claim 7, wherein a sidewall of the third through hole is coplanar with a sidewall of the fourth through hole.

### Claim 9 (depends on 1)

The package structure as claimed in claim 1, wherein the encapsulation layer is disposed between the redistribution layer and the active chip.

### Claim 10 (depends on 1)

The package structure as claimed in claim 1, wherein an aperture of the first through hole is less than an aperture of the second through hole.

### Claim 11 (depends on 1)

The package structure as claimed in claim 1, wherein the encapsulation layer comprises a photosensitive encapsulant material or a molding material.

### Claim 12 (depends on 1)

The package structure as claimed in claim 1, further comprising a chip and a plurality of conductive terminals disposed on a side of the redistribution layer away from the active chip and electrically connected to the redistribution layer.

### Claim 13 (depends on 1)

The package structure as claimed in claim 1, wherein a thickness of the active chip is greater than or equal to 200 micrometers.