# US 12,604,784 B2 · Stack packages and methods of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,784 B2 - Document ID: US12604784B2 - Status: Granted - Kind: B2 - Application number: 18/479,511 - Filed: 2023-10-02 - Published: 2024-01-25 - Granted: 2026-04-14 - Earliest claimed: 2021-03-09 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Ki Jun Sung; Chae Sung Lee - Web page: https://patentgrep.com/patent/US12604784B2 ## CPC - H10W 90/00: Package configurations - H10P 72/74: {using temporarily an auxiliary support} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/0198: {batch processes} - H10W 74/111: {the semiconductor body being completely enclosed} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 70/6528: {of the portions that connect to chips, wafers or package parts} - H10W 72/073: {of die-attach connectors} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A stack package, and a method of manufacturing the same, includes a first encapsulant layer formed on a carrier. Also semiconductor dies are sequentially offset stacked on the first encapsulant layer. Vertical connectors connected to the semiconductor dies are formed. A second encapsulant layer coupled to the first encapsulant layer is formed to encapsulate the vertical connectors and the semiconductor dies. Redistribution layers connected to the vertical connectors are formed on the second encapsulant layer. ## Claims ### Claim 1 A method of manufacturing a stack package, the method comprising: forming a first encapsulant layer on a carrier with a first adhesive layer directly therebetween; offset stacking semiconductor dies on the first encapsulant layer; forming vertical connectors connected to the semiconductor dies; forming a second encapsulant layer coupled to the first encapsulant layer and encapsulating the vertical connectors and the semiconductor dies; and forming redistribution layers connected to the vertical connectors on the second encapsulant layer, wherein forming the first encapsulant layer includes laminating a first encapsulant film to the carrier; wherein the first encapsulant film comprises an epoxy molding compound (EMC) film; and wherein the carrier and the first adhesive layer are removed from the first encapsulant layer and the EMC film remains coupled to the second encapsulant layer. ### Claim 2 (depends on 1) The method of claim 1, wherein the first encapsulant layer includes a cavity into which a lower semiconductor die among the stacked semiconductor dies is disposed. ### Claim 3 (depends on 1) The method of claim 1, wherein forming the second encapsulant layer includes forming the second encapsulant layer using a liquid EMC. ### Claim 4 (depends on 1) The method of claim 1, wherein disposing the lower semiconductor die on the first encapsulant layer comprises attaching the lower semiconductor die to the first encapsulant layer by a second adhesive layer. ### Claim 5 (depends on 1) The method of claim 1, wherein offset stacking the semiconductor dies further includes offset stacking a second intermediate semiconductor die of the semiconductor dies between the lower semiconductor die and the first intermediate semiconductor die with a third offset in substantially the same direction as the first offset. ### Claim 6 (depends on 5) The method of claim 5, wherein stacking the upper semiconductor die comprises positioning the upper semiconductor die to expose a portion of the second intermediate semiconductor die while exposing a portion of the first intermediate semiconductor die. ### Claim 7 (depends on 1) The method of claim 1, wherein forming the vertical connectors comprises forming the first bonding wire and forming the second bonding wire at positions opposite to each other with the upper semiconductor die interposed therebetween. ### Claim 8 (depends on 1) The method of claim 1, wherein forming the vertical connectors further includes forming conductive bumps connected to the upper semiconductor die. ### Claim 9 (depends on 1) The method of claim 1, wherein forming the redistribution layers further includes recessing the second encapsulant layer to expose end portions of the vertical connectors. ### Claim 10 (depends on 1) The method of claim 1, further comprising: forming connection terminals electrically connected to the redistribution layers; and removing the carrier. ### Claim 11 A method comprising: forming a first encapsulant layer on a carrier with a adhesive layer directly therebetween; disposing a first semiconductor die on the first encapsulant layer; stacking a second semiconductor die on the first semiconductor die with a first offset in a first direction; and stacking a third semiconductor die on the second semiconductor die with a second offset in second direction opposite to the first direction; and forming a first bonding wire connected to the first semiconductor die and extending substantially vertically past the third semiconductor die and the second semiconductor die; and forming a second bonding wire connected to the second semiconductor die and extending substantially vertically past the third semiconductor die; forming a second encapsulant layer encapsulating the first bonding wire, the second bonding wire, the first semiconductor die, the second semiconductor die, and the third semiconductor die, wherein forming the first encapsulant layer includes laminating a first encapsulant film to the carrier; wherein the first encapsulant film comprises an epoxy molding compound (EMC) film; and wherein the carrier and the adhesive layer are removed from the first encapsulant layer and the EMC film remains coupled to the second encapsulant layer. ### Claim 12 (depends on 11) The method of claim 11, further comprising forming, on the second encapsulant layer, redistribution layers connected to the first bonding wire and the second bonding wire. ### Claim 13 (depends on 11) The method of claim 11, wherein the third semiconductor die is between the first bonding wire and the second bonding wire. ### Claim 14 A method comprising: disposing a first semiconductor die on a first encapsulant layer; stacking a second semiconductor die on the first semiconductor die with a first offset in a first direction; and stacking a third semiconductor die on the second semiconductor die with a second offset in second direction opposite to the first direction; and forming a first bonding wire connected to the first semiconductor die and extending substantially vertically near a first side of the third semiconductor die; and forming a second bonding wire connected to the second semiconductor die and extending substantially vertically past a second side the third semiconductor die, wherein the first side is opposite the second side, wherein the first encapsulant layer is formed by laminating a first encapsulant film to a carrier with a adhesive layer directly therebetween; wherein the first encapsulant film comprises an epoxy molding compound (EMC) film; and wherein the carrier and the adhesive layer are removed from the first encapsulant layer and the EMC film remains coupled to the second encapsulant layer. ### Claim 15 (depends on 14) The method of claim 14, further comprising forming a second encapsulant layer encapsulating the first bonding wire, the second bonding wire, the first semiconductor die, the second semiconductor die, and the third semiconductor die. ### Claim 16 (depends on 15) The method of claim 15, further comprising forming, on the second encapsulant layer, redistribution layers connected to the first bonding wire and the second bonding wire. ### Claim 17 (depends on 14) The method of claim 14, wherein the first encapsulant layer includes a cavity into which the first semiconductor die is disposed. ### Claim 18 (depends on 14) The method of claim 14, further comprising stacking a fourth semiconductor die between the first semiconductor die and the second semiconductor die with a third offset in substantially the first direction.