# US 12,604,783 B2 · Semiconductor device including a hybrid bonding structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,783 B2 - Document ID: US12604783B2 - Status: Granted - Kind: B2 - Application number: 18/474,231 - Filed: 2023-09-26 - Published: 2025-03-27 - Granted: 2026-04-14 - Earliest claimed: 2023-09-26 - Assignees: Macronix International Co., Ltd. - Applicants: MACRONIX International Co., Ltd. - Inventors: Shao-En Chang; Tzung-Ting Han; Meng-Hsuan Weng; Chen-Yu Cheng - Web page: https://patentgrep.com/patent/US12604783B2 ## CPC - H10W 90/00: Package configurations - H10B 43/40: characterised by the peripheral circuit region - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00) - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 46/301: {for alignment} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring. ## Claims ### Claim 1 A semiconductor device, comprising: a substrate; a first device structure layer disposed on the substrate; an interconnect structure layer disposed on the first device structure layer, and electrically connected to the first device structure layer, wherein the interconnect structure layer comprises a plurality of first pads located at a surface of the interconnect structure layer; a second device structure layer disposed on the interconnect structure layer, wherein the second device structure layer comprises a plurality of second pads located at a surface of the second device structure layer; a pattern structure, disposed at a first interface between the interconnect structure layer and the second device structure layer; a first seal ring, disposed at the surface of the interconnect structure layer and surrounding the pattern structure; and a second seal ring, disposed at the surface of the second device structure layer and surrounding the pattern structure, wherein each of the first pads is connected to a corresponding second pad of the plurality of second pads, and the first seal ring is connected to the second seal ring. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein a width of the pattern structure is larger than a width of the first pad, and larger than a width of the second pad. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein a width of the first seal ring is greater than or equal to half of a width of the first pad and less than or equal to 3 times of the width of the first pad. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein a width of the second seal ring is greater than or equal to half of a width of the second pad and less than or equal to 3 times the width of the second pad. ### Claim 5 (depends on 1) The semiconductor device of claim 1, wherein a width of the pattern structure is greater than or equal to 4 times a width of the first pad, and greater than or equal to 4 times a width of the second pad. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein the pattern structure is not electrically connected to the interconnect structure layer and not electrically connected to the second device structure layer. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the pattern structure comprises a sign mark or an alignment mark. ### Claim 8 (depends on 1) The semiconductor device of claim 1, wherein the pattern structure is located in the interconnect structure layer. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein a distance between the first seal ring and the pattern structure is greater than or equal to 2 times a width of first pad. ### Claim 10 (depends on 1) The semiconductor device of claim 1, wherein the pattern structure is located in the second device structure layer. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein a distance between the second seal ring and the pattern structure is greater than or equal to 2 times a width of second pad. ### Claim 12 (depends on 1) The semiconductor device of claim 1, wherein the plurality of the first pads comprises at least one first electrically-connected pad and at least one first dummy pad, the plurality of the second pads comprises at least one second electrically-connected pad and at least one second dummy pad, each first electrically-connected pad is connected to a corresponding second electrically-connected pad of the at least one second electrically-connected pad, and each first dummy pad is connected to a corresponding second dummy pad of the at least one second dummy pad. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the first electrically-connected pad is electrically connected to the first device structure layer. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the second electrically-connected pad is electrically connected to the second device structure layer. ### Claim 15 (depends on 1) The semiconductor device of claim 1, wherein there is no first pad between the first seal ring and the pattern structure, and there is no second pad between the second seal ring and the pattern structure. ### Claim 16 (depends on 1) The semiconductor device of claim 1, wherein a width of the first seal ring is the same as a width of the second seal ring. ### Claim 17 (depends on 1) The semiconductor device of claim 1, wherein a width of the first seal ring is different from a width of the second seal ring. ### Claim 18 (depends on 1) The semiconductor device of claim 1, wherein there is a second interface between the first pad and the second pad. ### Claim 19 (depends on 1) The semiconductor device of claim 1, wherein the second device structure layer comprises a memory structure layer. ### Claim 20 (depends on 19) The semiconductor device of claim 19, wherein the memory structure layer comprises a three-dimensional (3D) flash memory structure.