# US 12,604,781 B2 · Package structure including guiding patterns

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- Number: US 12,604,781 B2
- Document ID: US12604781B2
- Status: Granted
- Kind: B2
- Application number: 18/324,989
- Filed: 2023-05-28
- Published: 2024-11-28
- Granted: 2026-04-14
- Earliest claimed: 2023-05-28
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Chen-Hsuan Tsai; Chin-Chuan Chang; Ying-Ching Shih
- Web page: https://patentgrep.com/patent/US12604781B2

## CPC

- H10W 90/00: Package configurations
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/611: {Bolts or screws}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 40/60: Securing means for detachable heating or cooling arrangements, e.g. clamps
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A package structure including a wiring substrate, semiconductor dies, and a dielectric layer is provided. The wiring substrate includes die bonding regions and guiding patterns (auxiliary patterns, or dummy patterns) distributed between the die bonding regions. The semiconductor dies are disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies. The dielectric layer is disposed the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns.

## Claims

### Claim 1

A package structure, comprising:
a wiring substrate comprising die bonding regions and guiding patterns distributed between the die bonding regions;
semiconductor dies disposed on the die bonding regions and electrically connected to the wiring substrate, wherein the guiding patterns are electrically insulated from the semiconductor dies; and
a dielectric layer between the semiconductor dies and the wiring substrate, wherein the dielectric layer covers and is in contact with the guiding patterns, wherein a minimum distance between the bonding regions and the semiconductor dies is greater than a thickness of the guiding patterns.

### Claim 2 (depends on 1)

The package structure of claim 1, wherein the guiding patterns are electrically floating.

### Claim 3 (depends on 1)

The package structure of claim 1, wherein the guiding patterns are electrically insulated from conductive wirings of the wiring substrate, and the conductive wirings of the wiring substrate are electrically connected to the semiconductor dies.

### Claim 4 (depends on 1)

The package structure of claim 1, wherein the guiding patterns comprise strip-shaped patterns extending from a first die bonding region among the die bonding regions to a second die bonding region among the die bonding regions.

### Claim 5 (depends on 1)

The package structure of claim 1, wherein the guiding patterns comprise dot-shaped patterns distributed between the die bonding regions.

### Claim 6 (depends on 1)

The package structure of claim 1, wherein the guiding patterns each comprises a conductive pattern and a solder material, the conductive pattern is disposed on the wiring substrate, and the solder material covers the conductive pattern.

### Claim 7 (depends on 1)

The package structure of claim 1, wherein the dielectric layer comprises an underfill, and the guiding patterns are spaced apart from the semiconductor dies by the underfill.

### Claim 8 (depends on 1)

The package structure of claim 1 further comprising:
an insulating encapsulation disposed on the wiring substrate and laterally encapsulating the semiconductor dies.

### Claim 9

A package structure, comprising:
a wiring substrate comprising bonding regions, the die bonding regions being laterally spaced apart from each other by a separation region, wherein the wiring substrate further comprising auxiliary patterns distributed in the separation region;
a first semiconductor die disposed on a first die bonding region among the die bonding regions and electrically connected to the wiring substrate, the first semiconductor die comprising a first group of conductive terminals and a second group of conductive terminals, and a first arrangement pitch of the first group of conductive terminals being greater than a second arrangement pitch of the second group of conductive terminals, wherein a height of the first group of conductive terminals is greater than a thickness of the auxiliary patterns; and
a dielectric layer disposed between the first semiconductor die and the wiring substrate, wherein the dielectric layer covers and is in contact with the auxiliary patterns.

### Claim 10 (depends on 9)

The package structure of claim 9 further comprising:
a second semiconductor die disposed on a second die bonding region among the die bonding regions and electrically connected to the wiring substrate, the second semiconductor die comprising a third group of conductive terminals and a fourth group of conductive terminals, a third arrangement pitch of the third group of conductive terminals being greater than a fourth arrangement pitch of the fourth group of conductive terminals, wherein the auxiliary patterns are electrically insulated from the first group of conductive terminals, the second group of conductive terminals, the third group of conductive terminals, and the fourth group of conductive terminals, and
the dielectric layer is further disposed between the second semiconductor die and the wiring substrate.

### Claim 11 (depends on 9)

The package structure of claim 9, wherein the auxiliary patterns are electrically floating or electrically insulated from the semiconductor dies.

### Claim 12 (depends on 9)

The package structure of claim 9, wherein the auxiliary patterns comprise strip-shaped patterns extending across the separation region.

### Claim 13 (depends on 9)

The package structure of claim 9, wherein the auxiliary patterns comprise dot-shaped patterns distributed in the separation region.

### Claim 14 (depends on 9)

The package structure of claim 9, wherein the auxiliary patterns each comprises a conductive pattern and a solder material, the conductive pattern is disposed on the wiring substrate, and the solder material covers the conductive pattern.

### Claim 15 (depends on 9)

The package structure of claim 9, wherein the first group of conductive terminals are laterally disposed between the auxiliary patterns and the second group of conductive terminals, and the third group of conductive terminals are laterally disposed between the auxiliary patterns and the fourth group of conductive terminals.

### Claim 16

A package structure, comprising:
a wiring substrate comprising conductive wirings and dummy patterns, wherein the dummy patterns are distributed on a surface of the wiring substrate and are electrically floating;
a first semiconductor die disposed on the surface of the wiring substrate and electrically connected to the conductive wirings of the wiring substrate, wherein a height of the dummy patterns is less than a standoff distance between the first semiconductor die and the surface of the wiring substrate;
a second semiconductor die disposed on the surface of the wiring substrate and electrically connected to the conductive wirings of the wiring substrate; and
a dielectric layer comprising a first portion, a second portion and a connecting portion between the first portion and the second portion, wherein the first portion is disposed between the first semiconductor die and the wiring substrate, the second portion is disposed between the second semiconductor die and the wiring substrate, the connecting portion of the dielectric layer covers and is in contact with the dummy patterns.

### Claim 17 (depends on 16)

The package structure of claim 16, wherein the dielectric layer comprises an underfill, and the dummy patterns are spaced apart from the semiconductor die by the underfill.

### Claim 18 (depends on 16)

The package structure of claim 16, wherein the connecting portion is thicker than the first portion and the second portion.

### Claim 19 (depends on 16)

The package structure of claim 16 further comprising:
first conductive terminals, wherein the first semiconductor die is electrically connected to the conductive wirings of the wiring substrate through the first conductive terminals; and
second conductive terminals, wherein the second semiconductor die is electrically connected to the conductive wirings of the wiring substrate through the second conductive terminals.

### Claim 20 (depends on 16)

The package structure of claim 16, wherein the dummy patterns each comprises a conductive pattern and a solder material, the conductive pattern is disposed on the wiring substrate, and the solder material covers the conductive pattern.