# US 12,604,775 B2 · Semiconductor chip and semiconductor package

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- Number: US 12,604,775 B2
- Document ID: US12604775B2
- Status: Granted
- Kind: B2
- Application number: 18/141,675
- Filed: 2023-05-01
- Published: 2024-02-08
- Granted: 2026-04-14
- Earliest claimed: 2022-08-03
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyeonmin Lee; Jihoon Kim; Aenee Jang
- Web page: https://patentgrep.com/patent/US12604775B2

## CPC

- H10W 90/00: Package configurations
- H10W 72/90: Bond pads, in general
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 72/01: {Manufacture or treatment}
- H10W 72/0198: {batch processes}
- H10W 72/921: {Structures or relative sizes of bond pads}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/936: {Multiple bond pads having different shapes}
- H10W 72/9445: {Top-view layouts, e.g. mirror arrays}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/953: {not comprising solid metals or solid metalloids, e.g. polymers, ceramics or liquids}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 80/334: {Thermocompression bonding}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/792: {between multiple chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads. The plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface. On a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from a top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads. From a top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than a second area.

## Claims

### Claim 1

A semiconductor package comprising:
a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads; and
a second semiconductor chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads,
wherein the plurality of wiring patterns include top wiring patterns adjacent to the plurality of first pads in a direction perpendicular to the front surface,
wherein, on a plane parallel to the front surface, within a first region having a first shape and first region area from a top down view, first top wiring patterns have a first occupied area between adjacent first pads of a first group of first pads from among the plurality of first pads, and within a second region having the first shape and first region area from the top down view, second top wiring patterns have a second occupied area, larger than the first occupied area, between adjacent first pads of a second group of first pads from among the plurality of first pads, and
wherein, from the top down view, each pad of the first group of first pads has a first area, and each pad of the second group of first pads has a second area, wherein the first area is smaller than the second area.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein:
the first occupied area is equal to a sum of areas of the top wiring patterns that are disposed in the first region, wherein the first region has at least a pair of first parallel sides, respectively passing through centers of corresponding adjacent first pads of the first group of first pads, and
the second occupied area is equal to a sum of areas of the top wiring patterns that are disposed in the second region, wherein the second region has at least a pair of second parallel sides, respectively passing through centers of corresponding adjacent first pads of the second group of first pads.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein:
centers of the first parallel sides match the centers of first pads of the first group of first pads, respectively, and
centers of the second parallel sides match the centers of first pads of the second group of first pads, respectively.

### Claim 4 (depends on 2)

The semiconductor package of claim 2, wherein:
a length of the first parallel sides is the same as a distance between the centers of two adjacent first pads of the first group of first pads, and
a length of the second parallel sides is the same as a distance between the centers of two adjacent first pads of the second group of first pads.

### Claim 5 (depends on 2)

The semiconductor package of claim 2, wherein:
a first ratio of the first area to the first occupied area and a second ratio of the second area to the second occupied area are each about 0.4 or less.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein:
the top wiring patterns include first contact patterns, respectively contacting first pads of the first group of first pads, second contact patterns, respectively contacting first pads of the second group of first pads, and at least one trace pattern disposed between adjacent second contact patterns.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein
the first semiconductor chip further includes a capping barrier layer extending between the first insulating layer and the top wiring patterns.

### Claim 8 (depends on 7)

The semiconductor package of claim 7, wherein:
the capping barrier layer includes at least one of silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbonitride (SiCN), aluminum nitride (AlN), aluminum oxynitride (AlON), aluminum oxide (AlO), or aluminum oxycarbide (AlOC).

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of first pads include copper (Cu) or a copper (Cu) alloy, and
the top wiring patterns include aluminum (Al) or an aluminum (Al) alloy.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein:
the first area of each pad of the first group of first pads is smaller than an area of each pad of the plurality of second pads.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein:
a contact area between each pad of the first group of first pads and each respective pad of the plurality of second pads is about 50% or more of the first area.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein:
the first insulating layer includes a lower insulating layer, contacting the second insulating layer, and an upper insulating layer disposed on the lower insulating layer.

### Claim 13 (depends on 12)

The semiconductor package of claim 12, wherein:
the lower insulating layer includes a silicon carbonitride (SiCN), and
the upper insulating layer and the second insulating layer include a silicon oxide (SiO).

### Claim 14 (depends on 1)

The semiconductor package of claim 1, wherein:
the plurality of first pads include a third group of first pads including pairs adjacent to each other, each first pad of the third group of first pads having a third area larger than the second area, and
within a region having the same shape and area as each of the first region and second region, the top wiring patterns include a third contact pattern having a third occupied area, larger than the second occupied area, between adjacent pads of the third group of first pads.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein:
the third group of first pads contact the third contact pattern.

### Claim 16

A semiconductor package comprising:
a first semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and top wiring patterns adjacent to the plurality of first pads between the first substrate and the plurality of first pads in a direction perpendicular to the front surface; and
a second chip disposed below the first semiconductor chip and including a second substrate, a plurality of second pads disposed on the second substrate and contacting the plurality of first pads, a second insulating layer surrounding the plurality of second pads and contacting the first insulating layer, and a plurality of through-electrodes penetrating through the second substrate to be connected to the plurality of second pads,
wherein the top wiring patterns include a set of first contact patterns contacting a first group of first pads, the first group of first pads including pairs of first pads adjacent to each other in a first direction parallel to the front surface, a set of second contact patterns contacting a second group of first pads, the second group of first pads including pairs of first pads adjacent to each other in the first direction, and at least one trace pattern disposed between adjacent contact patterns of the second contact patterns in the first direction, and
wherein each first pad of the first group of first pads has a first width in the first direction, and each pad of the second group of first pads has a second width in the first direction, wherein the first width is narrower than the second width.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein:
in the first direction, a first maximum width of each of the first contact patterns is the same as a second maximum width of each of the second contact patterns.

### Claim 18

A semiconductor package comprising:
at least one semiconductor chip including a first substrate, a plurality of first pads disposed on a front surface of the first substrate, a first insulating layer surrounding the plurality of first pads, and a plurality of wiring patterns disposed between the first substrate and the plurality of first pads and electrically connected to the plurality of first pads,
wherein the plurality of first pads include first pairs of first pads and second pairs of first pads, each first pad of each first pair having a first area from a plan view and each first pad of each second pair having a second area from the plan view, the second area being different from the first area;
wherein, within respective first reference regions in the plan view between two pads of respective first pairs of first pads adjacent to each other, respective first top wiring patterns adjacent to the respective first pairs of first pads in a direction perpendicular to the front surface have a first predetermined occupied area,
wherein, within respective second reference regions in the plan view between two pads of respective second pairs of first pads adjacent to each other, respective second top wiring patterns adjacent to the respective second pairs of first pads in a direction perpendicular to the front surface have a second predetermined occupied area,
wherein each first reference region has the same area and shape as each second reference region in the plan view,
wherein each first pair of first pads in a respective reference region in the plan view has an area within the respective reference region proportional to a respective first predetermined occupied area according to a first ratio, and
wherein each second pair of first pads in a respective reference region in the plan view has an area within the respective reference region proportional to a respective second predetermined occupied area according to the first ratio.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, wherein:
each first reference region has a pair of parallel first sides, respectively passing through centers of first pads of each first pair of first pads, and a pair of second sides connecting ends of the pair of first sides to each other and parallel to each other, and a length of the first sides is the same as a length of the second sides, and
each second reference region has a pair of parallel first sides, respectively passing through centers of first pads of each second pair of first pads, and a pair of second sides connecting ends of the pair of first sides to each other and parallel to each other, and a length of the first sides is the same as a length of the second sides.

### Claim 20 (depends on 18)

The semiconductor package of claim 18, wherein:
each predetermined occupied area is equal to a sum of areas of the top wiring patterns disposed in a respective reference region.