# US 12,604,768 B2 · Semiconductor package and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,768 B2 - Document ID: US12604768B2 - Status: Granted - Kind: B2 - Application number: 17/961,954 - Filed: 2022-10-07 - Published: 2023-04-13 - Granted: 2026-04-14 - Earliest claimed: 2021-10-13 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Choong Bin Yim; Ji Hwang Kim; Jin-Woo Park; Jong Bo Shim - Web page: https://patentgrep.com/patent/US12604768B2 ## CPC - H10W 90/00: Package configurations - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 74/01: Manufacture or treatment - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices - H10P 72/74: {using temporarily an auxiliary support} - H10P 72/7424: {used as a support during the manufacture of self-supporting substrates} - H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/222: {Multilayered bumps, e.g. a coating on top and side surfaces of a bump core} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/90: Bond pads, in general - H10W 90/20: Configurations of stacked chips - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip. ## Claims ### Claim 1 A semiconductor package, comprising: a first wiring structure, wherein the first wiring structure includes a first insulating layer and a first wiring pad inside the first insulating layer; a first semiconductor chip on the first wiring structure; a second wiring structure on the first semiconductor chip, wherein the second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer, wherein the second insulating layer and the plurality of second wiring pads each directly contact one surface of the first semiconductor chip; and a connecting member between the first wiring structure and the second wiring structure. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the plurality of second wiring pads are on the first semiconductor chip and are isolated from direct contact with each other in the second insulating layer. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the second wiring structure further includes a third wiring pad that is in the second insulating layer and directly contacts the connecting member. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein an upper surface of the connecting member is on a same plane as the one surface of the first semiconductor chip. ### Claim 5 (depends on 1) The semiconductor package of claim 1, wherein the connecting member includes a conductive substance which includes a first layer, and a second layer that surrounds the first layer. ### Claim 6 (depends on 5) The semiconductor package of claim 5, wherein the first wiring pad directly contacts the first layer and is isolated from direct contact with the second layer. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the connecting member includes an insulating substance. ### Claim 8 (depends on 1) The semiconductor package of claim 1, comprising: a first mold layer which covers the first semiconductor chip and the connecting member. ### Claim 9 (depends on 8) The semiconductor package of claim 8, wherein the one surface of the first semiconductor chip is isolated from direct contact with the first mold layer. ### Claim 10 (depends on 1) The semiconductor package of claim 1, further comprising: a second semiconductor chip placed on the second wiring structure; and a second mold layer which covers the second semiconductor chip. ### Claim 11 A semiconductor package, comprising: a first wiring structure which includes a first insulating layer and a first wiring pad inside the first insulating layer; a first semiconductor chip on the first wiring structure; a second wiring structure which is placed on the first semiconductor chip, wherein the second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip; a connecting member placed between the first wiring structure and the second wiring structure; and a mold layer which covers the first semiconductor chip, wherein the one surface of the first semiconductor chip is isolated from direct contact with the mold layer. ### Claim 12 (depends on 11) The semiconductor package of claim 11, wherein the plurality of second wiring pads are on the first semiconductor chip and are isolated from direct contact with each other in the second insulating layer. ### Claim 13 (depends on 11) The semiconductor package of claim 11, wherein the second wiring structure further includes a third wiring pad which is in the second insulating layer and directly contacts the connecting member. ### Claim 14 (depends on 11) The semiconductor package of claim 11, wherein an upper surface of the connecting member is on a same plane as the one surface of the first semiconductor chip. ### Claim 15 (depends on 11) The semiconductor package of claim 11, wherein the connecting member includes a first layer and a second layer which surrounds the first layer. ### Claim 16 A method of fabricating a semiconductor package, the method comprising: forming a first wiring structure, the first wiring structure including a first insulating layer and a first wiring pad inside the first insulating layer; forming a first semiconductor chip having a first thickness on the first wiring structure; forming a connecting member having a second thickness lower than the first thickness on the first wiring structure the first semiconductor chip; removing at least a part of the first semiconductor chip and the connecting member to expose one surface of the first semiconductor chip and one surface of the connecting member; and forming a second wiring structure on the first semiconductor chip, the second wiring structure including a second insulating layer and a plurality of second wiring pads inside the second insulating layer, the second insulating layer and the plurality of second wiring pads each directly contacting the one surface of the first semiconductor chip. ### Claim 17 (depends on 16) The method of fabricating the semiconductor package of claim 16, further comprising: forming a first mold layer which covers the first semiconductor chip and the connecting member, subsequent to forming the connecting member. ### Claim 18 (depends on 16) The method of fabricating the semiconductor package of claim 16, wherein the plurality of second wiring pads are on the first semiconductor chip and are isolated from direct contact with each other in the second insulating layer. ### Claim 19 (depends on 16) The method of fabricating the semiconductor package of claim 16, wherein the second wiring structure further includes a third wiring pad that is in the second insulating layer and directly contacts the connecting member. ### Claim 20 (depends on 16) The method of fabricating the semiconductor package of claim 16, wherein the one surface of the connecting member is placed on a same plane as the one surface of the first semiconductor chip.