# US 12,604,767 B2 · Chipset and method of manufacturing the same

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- Number: US 12,604,767 B2
- Document ID: US12604767B2
- Status: Granted
- Kind: B2
- Application number: 17/958,456
- Filed: 2022-10-03
- Published: 2023-04-27
- Granted: 2026-04-14
- Earliest claimed: 2021-10-25
- Assignees: Shanghai Biren Technology Co., Ltd
- Applicants: Shanghai Biren Technology Co., Ltd
- Inventors: Shiqun Gu; Zhou Hong; Linglan Zhang; Zheng Tian; Hongying Zhang; Peng Liu
- Web page: https://patentgrep.com/patent/US12604767B2

## CPC

- H10W 90/00: Package configurations
- H10D 1/68: Capacitors having no potential barriers
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/01: Manufacture or treatment
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 72/7428: {used to support diced chips prior to mounting}
- H10W 72/072: {of bump connectors}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/20: Configurations of stacked chips
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a chipset and a manufacturing method thereof. The chipset includes a logic chip, an input/output chip, and an interposer. The logic chip includes a plurality of first bonding components disposed in the first device layer. The input/output chip includes a plurality of second bonding components disposed in the second device layer. The interposer includes a plurality of third bonding components disposed in the third device layer. The logic chip is directly bonded to the first portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the first portion of the plurality of first bonding components, and the input/output chip is directly bonded to the second portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through the plurality of second bonding components.

## Claims

### Claim 1

A chipset, comprising:
a logic chip, having a first device layer and a first substrate layer, and comprising a plurality of first bonding components disposed in the first device layer;
an input/output chip, having a second device layer and a second substrate layer, and comprising a plurality of second bonding components disposed in the second device layer; and
an interposer, having a third device layer and a third substrate layer, and comprising a plurality of third bonding components disposed in the third device layer,
wherein the logic chip is directly bonded to a first portion of the plurality of third bonding components of the interposer in a pad-to-pad manner through a first portion of the plurality of first bonding components, and the input/output chip is directly bonded to a second portion of the plurality of third bonding components of the interposer in the pad-to-pad manner through the plurality of second bonding components,
wherein at least a portion of the first portion of the plurality of third bonding components is connected to at least a portion of the second portion of the plurality of third bonding components through a first metal wiring in the interposer,
wherein the third substrate layer of the interposer comprises a deep trench capacitor on one side adjacent to the third device layer, and the logic chip is directly bonded to a third portion of the plurality of third bonding components in the third device layer in the pad-to-pad manner through a second portion of the plurality of first bonding components, and the third portion of the plurality of third bonding components in the third device layer of the interposer is connected to the deep trench capacitor through a third metal wiring.

### Claim 2 (depends on 1)

The chipset according to claim 1, wherein the logic chip is bonded to the first portion of the plurality of third bonding components of the interposer in a hybrid bonding manner through the first portion of the plurality of first bonding components, and the input/output chip is bonded to the second portion of the plurality of third bonding components of the interposer in the hybrid bonding manner through the plurality of second bonding components,
wherein the plurality of first bonding components, the plurality of second bonding components and the plurality of third bonding components respectively comprise: a bonding pad, having a bonding surface;
a pillar, having one end connected to the bonding pad; and
a metal pad, connected with the other end of the pillar.

### Claim 3 (depends on 1)

The chipset according to claim 1, further comprising:
another logic chip, having a fourth device layer and a fourth substrate layer, and comprising a plurality of fourth bonding components disposed in the fourth device layer,
wherein the another logic chip is directly bonded to a fourth portion of the plurality of third bonding components of the interposer in the pad-to-pad manner through the plurality of fourth bonding components, and at least another portion of the first portion of the plurality of third bonding components is connected to at least a portion of the fourth portion of the plurality of third bonding components through a second metal wiring.

### Claim 4 (depends on 3)

The chipset according to claim 3, wherein the interposer comprises a plurality of through silicon vias (TSVs) penetrating the third substrate layer of the interposer and extending into at least a portion of the third device layer of the interposer, and the third portion of the plurality of third bonding components in the third device layer of the interposer is connected to the plurality of TSVs through a third metal wiring.

### Claim 5 (depends on 4)

The chipset according to claim 4, further comprising:
a redistribution layer, wherein the redistribution layer is connected with the plurality of TSVs of the interposer through a plurality of bumps.

### Claim 6 (depends on 5)

The chipset according to claim 5, further comprising:
a memory chip, connected to the redistribution layer through another plurality of bumps.

### Claim 7 (depends on 6)

The chipset according to claim 6, further comprising:
a molding, filled between the logic chip and the another logic chip, between the logic chip and the input/output chip, and between the input/output chip and the memory chip, wherein the molding is an organic material.

### Claim 8 (depends on 6)

The chipset according to claim 6, wherein the logic chip and the another logic chip are located at the center of the chipset, the input/output chip is arranged around the outside of the logic chip and the another logic chip, and the memory chip is located at the outside of the input/output chip.

### Claim 9 (depends on 3)

The chipset according to claim 3, wherein the logic chip and the input/output chip transmit data signals through the first metal wiring, and the logic chip and the another logic chip transmit the data signals through the second metal wiring.

### Claim 10 (depends on 1)

The chipset according to claim 1, wherein the first device layer of the logic chip comprises a first driving circuit on one side adjacent to the first substrate layer, and the first driving circuit is connected to the first portion of the plurality of first bonding components through a fourth metal wiring.

### Claim 11 (depends on 10)

The chipset according to claim 10, wherein the second device layer of the input/output chip comprises a second driving circuit on one side adjacent to the second substrate layer, and the second driving circuit is connected to at least a portion of the plurality of second bonding components through a fifth metal wiring.

### Claim 12 (depends on 11)

The chipset according to claim 11, wherein the first driving circuit and the second driving circuit are respectively multiplexer-free circuits.