# US 12,604,766 B2 · Semiconductor package structure

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- Number: US 12,604,766 B2
- Document ID: US12604766B2
- Status: Granted
- Kind: B2
- Application number: 17/934,233
- Filed: 2022-09-22
- Published: 2023-04-27
- Granted: 2026-04-14
- Earliest claimed: 2021-10-22
- Assignees: Mediatek Inc.
- Applicants: Mediatek Inc.
- Inventors: Hsiao-Yun Chen; Yao-Tsung Huang; Cheng-Jyi Chang
- Web page: https://patentgrep.com/patent/US12604766B2

## CPC

- H10D 1/665: {Trench conductor-insulator-semiconductor capacitors, e.g. trench MOS capacitors}
- H10W 90/00: Package configurations
- H10D 1/716: {having vertical extensions}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/01: {Manufacture or treatment}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 90/20: Configurations of stacked chips
- H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package structure includes a first redistribution layer, a first semiconductor die, a second through via, a molding material, a second semiconductor die, and a second redistribution layer. The first semiconductor die is disposed over the first redistribution layer and includes a first through via having a first width. The second through via is adjacent to the first semiconductor die and has a second width. The second width is greater than the first width. The molding material surrounds the first semiconductor die and the second through via. The second semiconductor die is disposed over the molding material and is electrically coupled to the first through via and the second through via. The second redistribution layer is disposed over the second semiconductor die.

## Claims

### Claim 1

A semiconductor package structure, comprising:
a first redistribution layer;
a first semiconductor die disposed over the first redistribution layer and comprising a first through via having a first width;
a second through via adjacent to the first semiconductor die and having a second width greater than the first width;
a molding material surrounding the first semiconductor die and the second through via;
a second semiconductor die disposed over the molding material and electrically coupled to the first through via and the second through via; and
a second redistribution layer disposed over the second semiconductor die,
wherein a bottom surface of the molding material is substantially level with a bottom surface of the first semiconductor die.

### Claim 2 (depends on 1)

The semiconductor package structure as claimed in claim 1, wherein the first width is 2 μm to 18 μm, and the second width is 40 μm to 80 μm.

### Claim 3 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a bump structure connecting the first semiconductor die and the second semiconductor die.

### Claim 4 (depends on 3)

The semiconductor package structure as claimed in claim 3, further comprising a third semiconductor die surrounded by the molding material, wherein the third semiconductor die comprises a third through via having a third width less than the second width.

### Claim 5 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a third redistribution layer disposed between the first semiconductor die and the second semiconductor die and electrically coupling the second semiconductor die to the first through via and the second through via.

### Claim 6 (depends on 5)

The semiconductor package structure as claimed in claim 5, further comprising a third semiconductor die surrounded by the molding material, wherein the third semiconductor die comprises a third through via having a third width less than the second width.

### Claim 7 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising an interposer disposed between the first redistribution layer and the second semiconductor die and comprising a deep trench capacitor.

### Claim 8 (depends on 7)

The semiconductor package structure as claimed in claim 7, wherein the interposer comprises the second through via.

### Claim 9 (depends on 7)

The semiconductor package structure as claimed in claim 7, further comprising a third redistribution layer disposed between the interposer and the second semiconductor die and electrically coupling the second semiconductor die to the deep trench capacitor.

### Claim 10 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a third through via disposed directly over the second through via and having a third width greater than the first width.

### Claim 11 (depends on 10)

The semiconductor package structure as claimed in claim 10, further comprising a third redistribution layer disposed between the first semiconductor die and the second semiconductor die and electrically coupled to the second semiconductor die, the first through via, the second through via, and the third through via.

### Claim 12 (depends on 1)

The semiconductor package structure as claimed in claim 1, further comprising a third through via disposed directly over the first semiconductor die and having a third width greater than the first width.

### Claim 13 (depends on 12)

The semiconductor package structure as claimed in claim 12, further comprising a third redistribution layer disposed between the second semiconductor die and the second through via and between the first semiconductor die and the third through via.

### Claim 14

A semiconductor package structure, comprising:
a first redistribution layer;
a first semiconductor die disposed over the first redistribution layer and comprising a first through via;
a second through via adjacent to the first semiconductor die;
a second semiconductor die disposed over a first portion of the first semiconductor die and electrically coupled to the first through via and the second through via;
a third through via disposed over a second portion of the first semiconductor die; and
a second redistribution layer disposed over the second semiconductor die and electrically coupled to the third through via.

### Claim 15 (depends on 14)

The semiconductor package structure as claimed in claim 14, wherein the first through via is disposed in the first portion of the first semiconductor die.

### Claim 16 (depends on 14)

The semiconductor package structure as claimed in claim 14, further comprising a molding material surrounding the first semiconductor die, the second semiconductor die, the second through via, and the third through via.

### Claim 17 (depends on 14)

The semiconductor package structure as claimed in claim 14, further comprising:
a third redistribution layer disposed between the first semiconductor die and the second semiconductor die;
a first molding material surrounding the first semiconductor die and the second through via; and
a second molding material surrounding the second semiconductor die and the third through via.

### Claim 18 (depends on 17)

The semiconductor package structure as claimed in claim 17, wherein the third through via electrically couples the third redistribution layer to the second redistribution layer.

### Claim 19

A semiconductor package structure, comprising:
a first redistribution layer;
a first semiconductor die disposed over the first redistribution layer;
an interposer disposed over the first redistribution layer and adjacent to the first semiconductor die, wherein the interposer comprises a through via and a deep trench capacitor;
a second semiconductor die disposed over the interposer and electrically coupled to the through via and the deep trench capacitor;
a molding material surrounding the first semiconductor die and the interposer; and
a second redistribution layer disposed over the second semiconductor die,
wherein a bottom surface of the molding material is substantially level with bottom surfaces of the first semiconductor die and the interposer.

### Claim 20 (depends on 19)

The semiconductor package structure as claimed in claim 19, further comprising a third redistribution layer disposed between the interposer and the second semiconductor die and electrically coupling the second semiconductor die to the deep trench capacitor.