# US 12,604,762 B2 · Methods and apparatus to reduce thickness of on-package memory architectures > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,762 B2 - Document ID: US12604762B2 - Status: Granted - Kind: B2 - Application number: 17/542,107 - Filed: 2021-12-03 - Published: 2023-06-08 - Granted: 2026-04-14 - Earliest claimed: 2021-12-03 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Eng Huat Goh; Jiun Hann Sir; Poh Boon Khoo - Web page: https://patentgrep.com/patent/US12604762B2 ## CPC - H10W 90/00: Package configurations - H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections - H10W 70/042: {Etching} - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 72/90: Bond pads, in general - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)} - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/811: {Multiple chips on leadframes} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Methods and apparatus to reduce thickness of on-package memory architectures are disclosed. An on-package memory architecture includes a memory die; a bonding pad including a first surface and a second surface opposite the first surface; a wire bond electrically coupling the memory die to the first surface of the bonding pad; and a metal stub protruding from the second surface of the bonding pad. The metal stub is to electrically couple with a contact pad on a package substrate of an integrated circuit (IC) package. ## Claims ### Claim 1 An apparatus comprising: a substrate; a processor die mounted to the substrate; a memory die mounted to the substrate, the memory die adjacent the processor die on a same side of the substrate as the processor die, the memory die including a first side and a second side opposite the first side, the first side of the memory die facing away from the substrate; a bonding pad, the memory die electrically coupled to a first surface of the bonding pad, the first surface of the bonding pad facing away from the substrate, the second side of the memory die closer to the substrate than the first surface of the bonding pad is to the substrate; and a metal stub protruding from a second surface of the bonding pad, the second surface opposite the first surface, an end of the metal stub soldered to a contact pad on the substrate. ### Claim 2 (depends on 1) The apparatus of claim 1, including an underfill material within gaps between the memory die and the substrate, the underfill material to surround the metal stub. ### Claim 3 (depends on 2) The apparatus of claim 2, including a mold compound to encapsulate the memory die, the mold compound different from the underfill material. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the memory die is encapsulated in a mold compound, a bottom surface of the mold compound to face toward a top surface of the substrate, the bottom surface of the mold compound less than 50 micrometers from the top surface of the substrate. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the bonding pad is encased in the mold compound. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the metal stub protrudes beyond the bottom surface of the mold compound. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the memory die, the bonding pad, and the metal stub are part of an on-package memory architecture, an overall thickness of the on-package memory architecture is within 10 micrometers of a thickness of the processor die. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the memory die is a first memory die, and the on-package memory architecture includes a mold compound that encases the first memory die and a second memory die stacked on the first memory die, the mold compound defining a bottom surface of the on-package memory architecture, the bottom surface to face towards the substrate, the first memory die to be closer to the substrate than the second memory die is to the substrate. ### Claim 9 (depends on 7) The apparatus of claim 7, including a heat spreader, the heat spreader having a single planar surface that is attached to both the on-package memory architecture and the processor die. ### Claim 10 (depends on 1) The apparatus of claim 1, including a wire bond electrically coupling the memory die to the first surface of the bonding pad. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the memory die is a first memory die, the apparatus including a second memory die stacked on the first memory die. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the bonding pad is a first bonding pad, and the metal stub is a first metal stub, the apparatus including: a second bonding pad spaced apart from the first bonding pad; and a second metal stub protruding from the second bonding pad. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the first metal stub is spaced apart from the second metal stub by a pitch of less than or equal to 110 micrometers. ### Claim 14 (depends on 12) The apparatus of claim 12, wherein the first bonding pad is laterally between the memory die and the second bonding pad. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the memory die, the bonding pad, and the metal stub are part of an on-package memory architecture, and the on-package memory architecture does not include a ball grid array. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein lateral sides of the on-package memory architecture are defined by a mold compound that encases the memory die, and the bonding pad is spaced apart from the lateral sides of the on-package memory architecture. ### Claim 17 (depends on 1) The apparatus of claim 1, wherein the memory die, the bonding pad, and the metal stub are part of an on-package memory architecture, and the on-package memory architecture does not include a package substrate to facilitate electrical coupling of the memory die to the substrate to which the processor die is mounted. ### Claim 18 (depends on 1) The apparatus of claim 1, including a metal plate extending in a plane aligned with the metal stub. ### Claim 19 An apparatus comprising: a substrate; a processor die carried by the substrate; a memory die carried by the substrate, the memory die adjacent the processor die on a same side of the substrate as the processor die; a bonding pad, the memory die electrically coupled to a first surface of the bonding pad; a metal stub protruding from a second surface of the bonding pad, the second surface opposite the first surface, an end of the metal stub soldered to a contact pad on the substrate; and a mold compound that encapsulates the memory die and all side walls of the bonding pad, the side walls extending between the first and second surfaces of the bonding pad. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the second surface of the bonding pad is flush with a bottom surface of the mold compound. ### Claim 21 (depends on 19) The apparatus of claim 19, wherein the metal stub is spaced apart from the mold compound. ### Claim 22 An apparatus comprising: a substrate; a processor die carried by the substrate; a memory die carried by the substrate, the memory die adjacent the processor die on a same side of the substrate as the processor die; a first bonding pad; and a second bonding pad, the memory die electrically coupled to at least one of the first bonding pad or the second bonding pad, the memory die laterally between the first bonding pad and the second bonding pad such that the memory die and the first and second bonding pads are in a common plane.