# US 12,604,759 B2 · Microelectronic assemblies including stiffeners around individual dies

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- Number: US 12,604,759 B2
- Document ID: US12604759B2
- Status: Granted
- Kind: B2
- Application number: 17/699,139
- Filed: 2022-03-20
- Published: 2023-09-21
- Granted: 2026-04-14
- Earliest claimed: 2022-03-20
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Pouya Talebbeydokhti; Mohan Prashanth Javare Gowda; Sonja Koller; Stephan Stoeckl; Thomas Wagner; Wolfgang Molzer
- Web page: https://patentgrep.com/patent/US12604759B2

## CPC

- H10W 76/12: characterised by their shape
- H10W 76/15: Containers comprising an insulating or insulated base
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 76/17: characterised by their materials
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 76/60: Seals
- H10W 90/00: Package configurations
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/072: {of bump connectors}
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 76/10: Containers or parts thereof
- H10W 76/63: characterised by their shape or disposition, e.g. between cap and walls of a container
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.

## Claims

### Claim 1

A microelectronic assembly, comprising:
a substrate;
a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and
a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate; wherein:
the substrate further includes a trench and the two or more sides of the lid are partially disposed in the trench, wherein a material of the trench includes a solder mask.

### Claim 2 (depends on 1)

The microelectronic assembly of claim 1, wherein the lid includes at least three sides.

### Claim 3 (depends on 1)

The microelectronic assembly of claim 1, wherein the lid includes at least four sides.

### Claim 4 (depends on 1)

The microelectronic assembly of claim 1, wherein a material of the lid includes a metal, a metal alloy, a plastic, or a ceramic.

### Claim 5 (depends on 1)

The microelectronic assembly of claim 1, wherein the material includes an underfill material.

### Claim 6 (depends on 1)

The microelectronic assembly of claim 1, wherein the material is between the substrate and the lid.

### Claim 7 (depends on 1)

The microelectronic assembly of claim 1, wherein the material is between the planar portion of the lid and the individual die.

### Claim 8 (depends on 1)

The microelectronic assembly of claim 1, wherein the two or more sides include cutouts.

### Claim 9 (depends on 1)

The microelectronic assembly of claim 1, wherein a bottom edge of the two or more sides includes a rail.

### Claim 10

A microelectronic assembly, comprising:
a package substrate;
a die having a first surface, an opposing second surface, a first side surface, and an opposing second side surface, wherein the first and second side surfaces extend between the first surface and the second surface, and wherein the first surface of the die is electrically coupled to the package substrate by interconnects;
a material surrounding the interconnects; and
a component having a surface, a first sidewall, and a second sidewall, wherein the first and second sidewalls extend from the surface of the component, wherein the surface of the component is coupled to the second surface of the die, wherein the first and second sidewalls of the component extend along the respective first and second side surfaces of the die towards the package substrate, and wherein:
the first and second sidewalls of the component are coupled to the package substrate by the material surrounding the interconnects; and
the substrate further includes a trench and the first and second sidewalls of the component are partially disposed in the trench, wherein a material of the trench includes a solder mask.

### Claim 11 (depends on 10)

The microelectronic assembly of claim 10, wherein the die further includes a third side surface extending between the first and second surfaces of the die, wherein the component further includes a third sidewall extending from the surface of the component, and wherein the third sidewall of the component extends along the third side surface of the die towards the package substrate and is coupled to the package substrate by the material surrounding the interconnects.

### Claim 12 (depends on 10)

The microelectronic assembly of claim 10, wherein the material includes an underfill material.

### Claim 13 (depends on 10)

The microelectronic assembly of claim 10, wherein the material is a first material, and the microelectronic assembly further comprises:
a second material between the surface of the component and the die.

### Claim 14 (depends on 13)

The microelectronic assembly of claim 13, wherein the second material includes a thermal interface material (TIM).

### Claim 15

A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package electrically coupled to the circuit board, wherein the IC package comprises:
a package substrate comprising a trench, wherein a material of the trench includes a solder mask;
a stiffener surrounding a single die, wherein the stiffener includes a planar portion and two or more sides extending from the planar portion and partially disposed in the trench, and wherein the single die is electrically coupled to the package substrate by interconnects; and
an underfill material surrounding the interconnects and coupling the two or more sides of the stiffener to the package substrate.

### Claim 16 (depends on 15)

The computing device of claim 15, wherein a thickness of the planar portion of the stiffener is between 200 microns and 400 microns.

### Claim 17 (depends on 15)

The computing device of claim 15, wherein a width of each of the two or more sides is between 200 microns and 400 microns.

### Claim 18 (depends on 15)

The computing device of claim 15, wherein a thickness of the material between the planar portion of the stiffener and the single die is between 25 microns and 50 microns.