# US 12,604,758 B2 · Chip packaging apparatus and preparation method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,758 B2 - Document ID: US12604758B2 - Status: Granted - Kind: B2 - Application number: 17/526,966 - Filed: 2021-11-15 - Published: 2022-03-10 - Granted: 2026-04-14 - Earliest claimed: 2019-05-15 - Assignees: Huawei Technologies Co., Ltd. - Applicants: Huawei Technologies Co., Ltd. - Inventors: Mao Guo; Yiwei Ren; Xiaodong Zhang - Web page: https://patentgrep.com/patent/US12604758B2 ## CPC - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)} - H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes} - H10W 74/014: {using batch processing} - H10W 72/0198: {batch processes} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/47: comprising organic materials, e.g. plastics or resins - H10W 90/721: {of bump connectors} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A chip packaging apparatus and a preparation method thereof are provided, to modulate warpage of a chip, thereby resolving a problem of mismatch between a warpage degree of the chip and a warpage degree of a substrate. The chip packaging apparatus includes a chip, a substrate, and a warpage modulation structure, where a surface that is of the chip and that faces the substrate is electrically connected to the substrate, the warpage modulation structure is disposed on a surface that is of the chip and that is opposite to the substrate, and a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip. ## Claims ### Claim 1 A chip packaging apparatus, comprising: a chip, a substrate, wherein a surface that is of the chip and that faces the substrate is electrically connected to the substrate by a plurality of bumps disposed between the chip and the substrate; a warpage modulation structure comprising a plurality of flexible portions having a similar height and width arranged in a parallel pattern, formed of one of a polyimide, or a phenolic aldehyde and is disposed on a surface that is of the chip and that is opposite to the substrate and bumps that connect the chip to the substrate, wherein a coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of the chip. ### Claim 2 (depends on 1) The chip packaging apparatus of claim 1, wherein the coefficient of thermal expansion of the warpage modulation structure is greater than a coefficient of thermal expansion of a metal layer of the chip. ### Claim 3 (depends on 1) The chip packaging apparatus of claim 1, wherein the warpage modulation structure comprises a plurality of first modulation strips arranged in a parallel pattern. ### Claim 4 (depends on 1) The chip packaging apparatus of claim 1, wherein the warpage modulation structure comprises two linearly disposed portions on the surface of the chip. ### Claim 5 (depends on 1) The chip packaging apparatus of claim 1, wherein the warpage modulation structure comprises a plurality of first modulation strips arranged in parallel and a plurality of second modulation strips arranged in parallel, and the plurality of first modulation strips respectively intersect with the plurality of second modulation strips in a diagonal pattern. ### Claim 6 (depends on 5) The chip packaging apparatus of claim 5, wherein the plurality of first modulation strips are respectively perpendicular to the plurality of second modulation strips. ### Claim 7 (depends on 6) The chip packaging apparatus of claim 6, wherein the plurality of first modulation strips are arranged with equal spacings, the plurality of first modulation strips are parallel to two edges of the chip, and the plurality of second modulation strips are arranged with equal spacings. ### Claim 8 (depends on 1) The chip packaging apparatus of claim 1, wherein the warpage modulation structure is a mesh-shaped structure, and the warpage modulation structure comprises a plurality of first modulation strips arranged in parallel and a plurality of second modulation strips arranged in parallel; the plurality of first modulation strips are respectively perpendicular to the plurality of second modulation strips, and the plurality of first modulation strips are parallel to two edges of the chip; and some second modulation strips in the plurality of second modulation strips intersect with some first modulation strips in the plurality of first modulation strips. ### Claim 9 (depends on 8) The chip packaging apparatus of claim 8, wherein the plurality of first modulation strips are arranged with equal spacings. ### Claim 10 (depends on 1) The chip packaging apparatus of claim 1, wherein a material of the warpage modulation structure is a polymer material. ### Claim 11 (depends on 1) The chip packaging apparatus of claim 1 wherein the warpage modulation structure is sized to be smaller than the chip. ### Claim 12 (depends on 1) The chip packaging apparatus of claim 1 wherein the warpage modulation structure is comprised of the polyimide. ### Claim 13 (depends on 1) The chip packaging apparatus of claim 1 wherein the warpage modulation structure is comprised of the phenolic aldehyde. ### Claim 14 A chip packaging apparatus, comprising: a chip, a substrate, wherein a surface that is of the chip and that faces the substrate is electrically connected to the substrate by a plurality of bumps disposed between the chip and the substrate; and a plurality of warpage modulation strips comprising flexible material having a similar height and width arranged in a parallel pattern, formed of one of a polyimide or a phenolic aldehyde that is disposed on a surface that is of the chip and that is opposite to the substrate and bumps that connect the chip to the substrate, wherein a coefficient of thermal expansion of the plurality of warpage modulation strips is greater than a coefficient of thermal expansion of the chip and wherein each of the plurality of warpage modulation strips are sized to be smaller than the chip.