# US 12,604,757 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,757 B2 - Document ID: US12604757B2 - Status: Granted - Kind: B2 - Application number: 17/986,995 - Filed: 2022-11-15 - Published: 2023-10-05 - Granted: 2026-04-14 - Earliest claimed: 2022-04-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Bo In Noh; Jeong Hoon Ahn; Yun Ki Choi - Web page: https://patentgrep.com/patent/US12604757B2 ## CPC - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation} - H10W 70/685: comprising multiple insulating layers - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/124: {the encapsulations having cavities other than that occupied by chips} - H10W 90/00: Package configurations - H10W 70/63: Vias, e.g. via plugs - H10W 72/072: {of bump connectors} - H10W 72/07252: {changes in structures or sizes} - H10W 72/073: {of die-attach connectors} - H10W 72/07352: {changes in structures or sizes} - H10W 72/07353: {changes in shapes} - H10W 72/221: {Structures or relative sizes} - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/321: {Structures or relative sizes of die-attach connectors} - H10W 72/332: {Plan-view shape, i.e. in top view} - H10W 72/334: {Cross-sectional shape, i.e. in side view} - H10W 72/387: {Flow barriers} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 74/10: characterised by their shape or disposition - H10W 74/127: {characterised by arrangements for sealing or adhesion} - H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 74/40: characterised by their materials - H10W 76/63: characterised by their shape or disposition, e.g. between cap and walls of a container - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes a circuit board, an interposer structure on the circuit board, a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other, and a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips. A slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees. ## Claims ### Claim 1 A semiconductor package comprising: a circuit board; an interposer structure on the circuit board; a first semiconductor chip and a second semiconductor chip on the interposer structure, the first and the second semiconductor chips electrically connected to the interposer structure and spaced apart from each other; a mold layer between the first and second semiconductor chips, the mold layer separating the first and second semiconductor chips; and an underfill between the interposer structure and the first semiconductor chip, wherein a slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, wherein an angle defined by a bottom side of the mold layer and the side wall of the mold layer is less than or equal to ninety degrees, wherein a slope of a side wall of the underfill is constant as the side wall of the underfill extends away from the upper side of the interposer structure, and wherein an angle defined by a bottom side of the underfill and a side wall of the underfill is greater than or equal to ninety degrees. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein an upper side of the mold layer is on a same plane as upper sides of the first and second semiconductor chips. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the first semiconductor chip is a logic chip, and the second semiconductor chip is a memory chip. ### Claim 4 (depends on 1) The semiconductor package of claim 1, wherein a height from an upper side of the mold layer to the upper side of the interposer structure is greater than a height from an upper side of the first semiconductor chip to the upper side of the interposer structure. ### Claim 5 (depends on 1) The semiconductor package of claim 1, further comprising: a heat slug on the circuit board, the heat slug covering the first and second semiconductor chips. ### Claim 6 (depends on 5) The semiconductor package of claim 5, further comprising: an adhesive layer between the mold layer and the heat slug, the adhesive layer bonding the mold layer and the heat slug to each other. ### Claim 7 (depends on 1) The semiconductor package of claim 1, further comprising: a first connecting member electrically connecting the circuit board and the interposer structure, and a second connecting member electrically connecting the interposer structure and the first semiconductor chip, wherein a size of the first connecting member is greater than a size of the second connecting member. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the interposer structure comprises: an interposer; an interlayer insulating layer on the interposer; redistribution layers inside the interlayer insulating layer, the redistribution layers electrically connected to the first and second semiconductor chips; and a through via penetrating the interposer, the through via connected to the redistribution layer. ### Claim 9 A semiconductor package comprising: a circuit board; an interposer structure on the circuit board; a mold layer on the interposer structure, wherein the mold layer defines a first trench and a plurality of second trenches around the first trench, an area of a cross section of the first trench from a planar viewpoint is greater than an area of a cross section of any one of the plurality of second trenches from the planar viewpoint, a slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, an angle defined by a side wall of the first trench and a bottom side of the first trench is greater than or equal to ninety degrees, and an angle defined by a side wall of at least one of the plurality of second trenches and a bottom side of the at least one of the plurality of second trenches is less than or equal to ninety degrees; a logic chip in the first trench, the logic chip electrically connected to the interposer structure; and a memory chip in at least one of the plurality of second trenches, the memory chip electrically connected to the interposer structure. ### Claim 10 (depends on 9) The semiconductor package of claim 9, wherein the cross section of the first trench and the cross sections of the plurality of second trenches each define at least one of a circle shape, a rectangle shape, a hexagon shape, and an octagon shape, from a planar viewpoint. ### Claim 11 (depends on 9) The semiconductor package of claim 9, wherein a ratio of a number of logic chips of the semiconductor package including the logic chip, to a number of memory chips of the semiconductor package including the memory chip, is less than or equal to one to four. ### Claim 12 (depends on 9) The semiconductor package of claim 9, wherein a height from an upper side of the mold layer to an upper side of the interposer structure is greater than a height from an upper side of the logic chip to the upper side of the interposer structure. ### Claim 13 (depends on 9) The semiconductor package of claim 9, wherein an upper side of the mold layer is on a same plane as the upper side of the logic chip and the upper side of the memory chip. ### Claim 14 (depends on 9) The semiconductor package of claim 9, further comprising: a first connecting member electrically connecting the circuit board and the interposer structure, and a second connecting member electrically connecting the interposer structure and the logic chip, wherein a size of the first connecting member is greater than a size of the second connecting member. ### Claim 15 (depends on 9) The semiconductor package of claim 9, further comprising: a heat slug on the circuit board, the heat slug covering the logic chip and the memory chip. ### Claim 16 (depends on 9) The semiconductor package of claim 9, further comprising: an underfill between the interposer structure and the logic chip, wherein a slope of a side wall of the underfill is constant as the side wall extends away from the upper side of the interposer structure, and an angle defined by a bottom side of the underfill and the side wall of the underfill is greater than or equal to ninety degrees. ### Claim 17 A semiconductor package comprising: a circuit board; an interposer structure on the circuit board; a mold layer on the interposer structure, the mold layer defining a first trench and a plurality of second trenches around the first trench; a logic chip in the first trench, the logic chip electrically connected to the interposer structure; a memory chip in at least one of the plurality of second trenches, the memory chip electrically connected to the interposer structure; a first connecting member between the circuit board and the interposer structure, the first connecting member electrically connecting the circuit board and the interposer structure; a second connecting member between the interposer structure and the logic chip, the second connecting member electrically connecting the interposer structure and the logic chip; a third connecting member between the interposer structure and the memory chip, the third connecting member electrically connecting the interposer structure and the memory chip; and a heat slug on the circuit board, the heat slug covering the logic chip and the memory chip, wherein the interposer structure includes an interposer, an interlayer insulating layer on the interposer, redistribution layers in the interlayer insulating layer, and a through via connected to the redistribution layer, and the redistribution layers are electrically connected to the logic chip and the memory chip, wherein an area of a cross section of the first trench from a planar viewpoint is greater than an area of a cross section of any one of the plurality of the second trenches from a planar viewpoint, a size of the first connecting member is greater than a size of the second connecting member and a size of the third connecting member, a slope of a side wall of the mold layer is constant as the side wall extends away from an upper side of the interposer structure, and an upper side of the mold layer is on a same plane as an upper side of the logic chip and an upper side of the memory chip. ### Claim 18 (depends on 17) The semiconductor package of claim 17, wherein an angle defined by a side wall of the first trench and a bottom side of the first trench is greater than or equal to ninety degrees, and an angle defined by a side wall of the at least one of the plurality of second trenches and a bottom side of the at least one of the plurality of second trenches is greater than or equal to ninety degrees. ### Claim 19 (depends on 17) The semiconductor package of claim 17, wherein the cross section of the first trench and the cross sections of the plurality of second trenches each define at least one of a circle shape, a rectangle shape, a hexagon shape, and an octagon shape, from a planar viewpoint.