# US 12,604,755 B2 · Semiconductor device interconnects formed through volumetric expansion > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,755 B2 - Document ID: US12604755B2 - Status: Granted - Kind: B2 - Application number: 18/199,741 - Filed: 2023-05-19 - Published: 2024-02-29 - Granted: 2026-04-14 - Earliest claimed: 2022-08-28 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Kyle K. Kirby; Terrence B. McDaniel; Wei Zhou - Web page: https://patentgrep.com/patent/US12604755B2 ## CPC - H10W 72/90: Bond pads, in general - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 72/931: {Shapes of bond pads} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/951: {Materials of bond pads} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W 80/312: {characterised by the direct bonding of electrically conductive pads} - H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers} - H10W 80/701: {characterised by the pads after the direct bonding} - H10W 80/732: {having shape changed during the connecting} - H10W 90/792: {between multiple chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract This document discloses techniques, apparatuses, and systems for semiconductor device interconnects formed through volumetric expansion. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die and the second semiconductor die are bonded at a dielectric layer of the first semiconductor die and a dielectric layer of the second semiconductor die to create one or more interconnect openings. The first semiconductor die includes a reservoir of conductive material located adjacent to the one or more interconnect openings and having a width greater than a width of the one or more interconnect openings. The reservoir of conductive material is heated to volumetrically expand the reservoir of conductive material through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. In this way, a connected semiconductor device may be assembled. ## Claims ### Claim 1 A method of making a semiconductor device assembly, comprising: providing a first semiconductor die including: a first dielectric layer having one or more first openings with a first width; and a first reservoir of conductive material located adjacent to the one or more first openings, the first reservoir of conductive material having a second width greater than the first width; providing a second semiconductor die including a second dielectric layer having one or more second openings corresponding to the one or more first openings; aligning the first dielectric layer and the second dielectric layer such that the one or more first openings align with the one or more second openings to create one or more interconnect openings; heating the first dielectric layer, the second dielectric layer, and the first reservoir of conductive material effective to: bond the first dielectric layer and the second dielectric layer; and cause the first reservoir of conductive material to volumetrically expand through the one or more interconnect openings to form one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. ### Claim 2 (depends on 1) The method of claim 1, wherein: the one or more second openings have a third width; the second semiconductor die further includes a second reservoir of conductive material located adjacent to the one or more second openings, the second reservoir of conductive material having a fourth width greater than the third width; and the method further includes heating the second reservoir of conductive material effective to cause the second reservoir of conductive material to volumetrically expand through the one or more interconnect openings to form the one or more interconnects electrically coupling the first semiconductor die and the second semiconductor die. ### Claim 3 (depends on 2) The method of claim 2, wherein the second width is different than the fourth width. ### Claim 4 (depends on 1) The method of claim 1, wherein: the one or more first openings include a plurality of first openings; the one or more interconnect openings include a plurality of interconnect openings; and the one or more interconnects include a plurality of redundant interconnects. ### Claim 5 (depends on 1) The method of claim 1, wherein: the plurality of first openings span a fifth width; and the second width is greater than the fifth width. ### Claim 6 (depends on 1) The method of claim 1, wherein the first reservoir of conductive material is volumetrically expanded in more than one dimension. ### Claim 7 (depends on 1) The method of claim 1, wherein the first semiconductor die includes internal circuitry coupled to the first reservoir of conductive material. ### Claim 8 (depends on 1) The method of claim 1, wherein the first reservoir of conductive material is located partially within the one or more first openings. ### Claim 9 A semiconductor device assembly, comprising: a first semiconductor die including: a first dielectric layer having a first opening with a first width; and a first continuous reservoir of conductive material including a first portion located adjacent to the first opening and a second portion extending through the first opening, the first portion of the first continuous reservoir of conductive material having a second width substantially greater than the first width; and a second semiconductor die including: a second dielectric layer having a second opening with a third width, the second opening corresponding to the first opening; and a second continuous reservoir of conductive material including a first portion located adjacent to the second opening and a second portion extending through the second opening, the first portion of the second continuous reservoir of conductive material having a fourth width substantially greater than the third width, wherein the first dielectric layer and the second dielectric layer are bonded at a bond line, and wherein the first continuous reservoir of conductive material and the second continuous reservoir of conductive material bond at the bond line to form an interconnect electrically coupling the first semiconductor die and the second semiconductor die. ### Claim 10 (depends on 9) The semiconductor device assembly of claim 9, wherein the second width is different from the fourth width. ### Claim 11 (depends on 9) The semiconductor device assembly of claim 9, wherein the conductive material includes copper. ### Claim 12 (depends on 9) The semiconductor device assembly of claim 9, wherein the second portion of the first continuous reservoir of conductive material or the second portion of the second continuous reservoir of conductive material has a first thickness between 0.5 microns and 10 microns. ### Claim 13 (depends on 9) The semiconductor device assembly of claim 9, wherein the first opening or the second opening has a depth between 0.001 microns and 1 micron. ### Claim 14 (depends on 9) The semiconductor device assembly of claim 9, wherein the first continuous reservoir of conductive material is asymmetric about an axis defined by the first width of the first opening. ### Claim 15 A semiconductor device assembly, comprising: a first semiconductor die including: a first dielectric layer having a plurality of openings spanning a first width; and a continuous reservoir of conductive material including a first portion located adjacent to the plurality of openings and a second portion extending through the plurality of openings, the first portion of the continuous reservoir of conductive material having a second width greater than the first width; and a second semiconductor die including a second dielectric layer having a plurality of contact pads corresponding to the first plurality of openings, wherein the first dielectric layer and the second dielectric layer are bonded, and wherein the continuous reservoir of conductive material and the plurality of contact pads couple to form a plurality of redundant interconnects electrically coupling the first semiconductor die and the second semiconductor die. ### Claim 16 (depends on 15) The semiconductor device assembly of claim 15, wherein the conductive material includes copper. ### Claim 17 (depends on 15) The semiconductor device assembly of claim 15, wherein the second portion of the continuous reservoir of conductive material has a first thickness between 0.5 microns and 10 microns. ### Claim 18 (depends on 15) The semiconductor device assembly of claim 15, wherein the plurality of openings have a depth between 0.001 microns and 1 micron. ### Claim 19 (depends on 15) The semiconductor device assembly of claim 15, wherein the first semiconductor die includes internal circuitry coupled to the continuous reservoir of conductive material. ### Claim 20 (depends on 15) The semiconductor device assembly of claim 15, wherein the second semiconductor die includes internal circuitry coupled to the plurality of contact pads.