# US 12,604,751 B2 · Semiconductor package

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- Number: US 12,604,751 B2
- Document ID: US12604751B2
- Status: Granted
- Kind: B2
- Application number: 17/851,129
- Filed: 2022-06-28
- Published: 2023-01-05
- Granted: 2026-04-14
- Earliest claimed: 2021-07-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Hyeonjun Song; Taehyeong Kim; Sangyoung Kim
- Web page: https://patentgrep.com/patent/US12604751B2

## CPC

- H10W 70/69: Insulating materials thereof
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 90/00: Package configurations
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/01: {Manufacture or treatment}
- H10W 72/072: {of bump connectors}
- H10W 72/07353: {changes in shapes}
- H10W 72/334: {Cross-sectional shape, i.e. in side view}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/90: Bond pads, in general
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 74/40: characterised by their materials
- H10W 90/20: Configurations of stacked chips
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a base chip including a passivation layer on an upper surface thereof, a semiconductor chip on the base chip, a bump on a lower surface of the semiconductor chip, an underfill layer covering the bump and covering the lower surface of the semiconductor chip, an encapsulant covering the semiconductor chip on the base chip, and an organic material layer on the passivation layer, wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

## Claims

### Claim 1

A semiconductor package comprising:
a base chip including a passivation layer on an upper surface thereof;
a semiconductor chip on the base chip;
a bump on a lower surface of the semiconductor chip;
an underfill layer covering the bump and covering the lower surface of the semiconductor chip;
an encapsulant covering the semiconductor chip on the base chip; and
an organic material layer on the passivation layer, an uppermost surface in a vertical direction of the organic material layer contacting the encapsulant, the vertical direction perpendicular the upper surface of the base chip,
wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the underfill layer and a second region, surrounding the first region, and the organic material layer is on the second region.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the organic material layer includes a material different from that of the passivation layer.

### Claim 3 (depends on 2)

The semiconductor package of claim 2, wherein the organic material layer includes a photosensitive polyimide (PSPI), and the passivation layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein the organic material layer includes a material different from those of the underfill layer and the encapsulant.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, wherein the organic material layer includes a photosensitive polyimide (PSPI) and the encapsulant includes an epoxy molding compound (EMC).

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the uppermost surface of the organic material layer is to be lower than a height of the lower surface of the semiconductor chip.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein a thickness of the organic material layer ranges from about 200 nm to about 400 nm.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the organic material layer is in contact with the base chip and the encapsulant.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, wherein
the underfill layer covers at least a portion of a side surface of the semiconductor chip,
a side surface of the organic material layer is in contact with the underfill layer, and
a lower surface of the organic material layer is in contact with the base chip.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein a void is on one side of the underfill layer on the first region adjacent to the second region.

### Claim 11 (depends on 10)

The semiconductor package of claim 10, wherein the void is in contact with a portion of a side surface of the organic material layer on the second region.

### Claim 12 (depends on 1)

The semiconductor package of claim 1, wherein the underfill layer covers at least a portion of the uppermost surface of the organic material layer adjacent to a side surface of the organic material layer.

### Claim 13 (depends on 1)

The semiconductor package of claim 1, wherein a bottom of the base chip includes a device layer.

### Claim 14

A semiconductor package comprising:
a first semiconductor chip having a first region and a second region, surrounding the first region, the first semiconductor chip including a passivation layer on an upper surface thereof;
a semiconductor structure including a second semiconductor chip on the first region of the first semiconductor chip;
a bump on a lower surface of the semiconductor structure;
an underfill layer covering a region in which the first semiconductor chip and the semiconductor structure overlap each other in the first region and covering at least a portion of a lower end of a side surface of the semiconductor structure;
a first organic material layer surrounding a side surface of the underfill layer on the second region; and
an encapsulant covering the semiconductor structure on the first semiconductor chip, an uppermost surface in a vertical direction of the first organic material layer contacting the encapsulant, the vertical direction parallel to a side surface of the first semiconductor chip,
wherein the first semiconductor chip has an area larger than that of the second semiconductor chip in plan view, and
wherein the first semiconductor chip includes silicon (Si), the passivation layer contacts the underfill layer on the first region, and the first organic material layer is on the second region.

### Claim 15 (depends on 14)

The semiconductor package of claim 14, wherein
the first organic material layer includes a photosensitive polyimide (PSPI), and
the first organic material layer includes a material different from a material of the first semiconductor chip and a material of the encapsulant.

### Claim 16 (depends on 14)

The semiconductor package of claim 14, wherein
the semiconductor structure further includes at least one third semiconductor chip on the second semiconductor chip, and
the second semiconductor chip and the at least one third semiconductor chip are dynamic random access memory (DRAM) chips.

### Claim 17 (depends on 14)

The semiconductor package of claim 14, wherein
the semiconductor structure further includes at least one third semiconductor chip on the second semiconductor chip, and
the second semiconductor chip has an area larger than that of the at least one third semiconductor chip in plan view, and
wherein the semiconductor package further includes a second organic material layer surrounding at least a portion including a lower end of a side surface of the at least one third semiconductor chip on the second semiconductor chip.

### Claim 18

A semiconductor package comprising:
a package substrate;
an interposer substrate on the package substrate and including a silicon (Si) layer;
a first semiconductor structure on the interposer substrate;
a second semiconductor structure adjacent to the first semiconductor structure on the interposer substrate, the second semiconductor structure including
a base chip including a passivation layer on an upper surface thereof,
a semiconductor chip on the base chip,
a first semiconductor structure bump on a lower surface of the semiconductor chip,
a first semiconductor structure underfill layer covering the first semiconductor structure bump and covering the lower surface of the semiconductor chip,
an encapsulant covering the semiconductor chip on the base chip, and
a first semiconductor structure organic material layer on the passivation layer, an uppermost surface in a vertical direction of the first semiconductor structure organic material layer contacting the encapsulant, the vertical direction perpendicular the upper surface of the base chip,
wherein the base chip includes silicon (Si), the passivation layer has a first region in contact with the first semiconductor structure underfill layer and a second region, surrounding the first region, and the first semiconductor structure organic material layer is on the second region; and
an interposer encapsulant covering the first semiconductor structure and the second semiconductor structure on the interposer substrate,
wherein an upper surface of the interposer substrate has a first region in which the first semiconductor structure and the second semiconductor structure are mounted and a remaining second region, and
the interposer substrate further includes an interposer organic material layer on the remaining second region and including a photosensitive polyimide (PSPI), an uppermost surface in a vertical direction of the interposer organic material layer contacting the interposer encapsulant, the vertical direction perpendicular the upper surface of the interposer substrate.

### Claim 19 (depends on 18)

The semiconductor package of claim 18, further comprising:
a bump on a lower surface of each of the first and second semiconductor structures and electrically connected to the interposer substrate; and
an underfill layer covering the bump.

### Claim 20 (depends on 19)

The semiconductor package of claim 19, wherein
the underfill layer includes a first underfill layer on the lower surface of the first semiconductor structure and a second underfill layer on the lower surface of the second semiconductor structure,
the first underfill layer covers at least a portion including the lower surface of the first semiconductor structure and a lower end of a side surface of the first semiconductor structure,
the second underfill layer covers at least a portion including the lower surface of the second semiconductor structure and a lower end of a side surface of the second semiconductor structure, and
the interposer organic material layer is spaced apart from the first and second semiconductor structures and in contact with the first and second underfill layers.