# US 12,604,749 B2 · Semiconductor package > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,749 B2 - Document ID: US12604749B2 - Status: Granted - Kind: B2 - Application number: 18/203,130 - Filed: 2023-05-30 - Published: 2024-03-07 - Granted: 2026-04-14 - Earliest claimed: 2022-09-02 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Kyuhyeon Choi - Web page: https://patentgrep.com/patent/US12604749B2 ## CPC - H10W 70/66: Conductive materials thereof - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/68: Shapes or dispositions thereof - H10W 70/685: comprising multiple insulating layers - H10W 72/072: {of bump connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/30: Die-attach connectors - H10W 72/50: Bond wires - H10W 72/851: {Dispositions of multiple connectors or interconnections} - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 90/00: Package configurations - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 99/00: Subject matter not provided for in other groups of this subclass - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/354: {comprising polymers} - H10W 72/865: {Die-attach connectors and bond wires} - H10W 72/877: {Bump connectors and die-attach connectors} - H10W 90/20: Configurations of stacked chips - H10W 90/24: at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/752: {between stacked chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor package includes: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer and a cavity; an adhesive layer disposed in the cavity; a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein connection pads are disposed on the first surface of the semiconductor chip and are electrically connected to the lower wiring layer, and wherein the second surface of the semiconductor chip is attached to the adhesive layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer; an encapsulant at least partially surrounding at least a portion of each of the semiconductor chip and the connection structure; and connection bumps electrically connected to the lower wiring layer. ## Claims ### Claim 1 A semiconductor package comprising: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer and a cavity that has a bottom surface facing the lower substrate; an adhesive layer disposed in the cavity; a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein first connection pads are disposed on the first surface of the semiconductor chip and are electrically connected to the upper wiring layer, and wherein the second surface of the semiconductor chip is attached to the adhesive layer; a lower adhesive layer attached to the first surface of the semiconductor chip; a lower semiconductor chip having a third surface and a fourth surface opposite the third surface, wherein second connection pads are disposed on the third surface of the lower semiconductor chip and are electrically connected to the lower wiring layer, and wherein the fourth surface is attached to the lower adhesive layer; a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other; an encapsulant filling a gap between the lower semiconductor chip and the lower substrate and at least partially surrounding at least a portion of each of the semiconductor chip, the lower semiconductor chip, and the connection structure; and connection bumps disposed below the lower substrate and electrically connected to the lower wiring layer. ### Claim 2 (depends on 1) The semiconductor package of claim 1, wherein the adhesive layer is in direct contact with the bottom surface of the cavity and the second surface of the semiconductor chip. ### Claim 3 (depends on 1) The semiconductor package of claim 1, wherein the upper substrate has a lower surface positioned at a level lower than a level of the bottom surface of the cavity, wherein a distance between the lower surface of the upper substrate and the bottom surface of the cavity corresponds to a height of the cavity, and a thickness of the adhesive layer in a direction, substantially perpendicular to the bottom surface, is equal to or greater than the height of the cavity. ### Claim 4 (depends on 3) The semiconductor package of claim 3, wherein the thickness of the adhesive layer is in a range of about 10 μm to about 100 μm. ### Claim 5 (depends on 3) The semiconductor package of claim 3, wherein a height of the cavity is in a range of about 10 μm to about 50 μm. ### Claim 6 (depends on 1) The semiconductor package of claim 1, wherein a first width of the adhesive layer in a direction, parallel to the bottom surface of the cavity, is equal to or greater than a second width of the semiconductor chip. ### Claim 7 (depends on 1) The semiconductor package of claim 1, wherein the cavity has a side surface connected to the bottom surface of the cavity, and the adhesive layer is in contact with the side surface of the cavity. ### Claim 8 (depends on 1) The semiconductor package of claim 1, wherein the semiconductor chip has a side surface between the first surface and the second surface, and the adhesive layer is in contact with at least a portion of the side surface of the semiconductor chip. ### Claim 9 (depends on 1) The semiconductor package of claim 1, wherein the adhesive layer includes a thermosetting resin, a thermoplastic resin, or a mixture thereof. ### Claim 10 (depends on 1) The semiconductor package of claim 1, wherein the lower semiconductor chip is connected to the lower wiring layer of the lower substrate through a bump structure. ### Claim 11 (depends on 10) The semiconductor package of claim 10, wherein each of the connection structure and the bump structure includes tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or alloys thereof. ### Claim 12 A semiconductor package comprising: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer and a protective layer that covers at least a portion of the upper wiring layer and that has a cavity facing the lower substrate; an adhesive layer attached within the cavity of the upper substrate; a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein first connection pads are disposed on the first surface of the semiconductor chip and are electrically connected to the upper wiring layer, and wherein the second surface of the semiconductor chip is attached to the adhesive layer; a lower adhesive layer attached to the first surface of the semiconductor chip; a lower semiconductor chip having a third surface and a fourth surface opposite the third surface, wherein second connection pads are disposed on the third surface of the lower semiconductor chip and are electrically connected to the lower wiring layer, and wherein the fourth surface is attached to the lower adhesive layer; and a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other. ### Claim 13 (depends on 12) The semiconductor package of claim 12, wherein the protective layer provides a lower surface of the upper substrate and a bottom surface of the cavity. ### Claim 14 (depends on 13) The semiconductor package of claim 13, wherein the bottom surface of the cavity is located on a level higher than a level of the lower surface of the upper substrate. ### Claim 15 (depends on 12) The semiconductor package of claim 12, wherein a height of the cavity is equal to or less than a thickness of the protective layer. ### Claim 16 (depends on 12) The semiconductor package of claim 12, wherein the protective layer includes a first protective layer and a second protective layer, wherein the first protective layer is disposed on the upper wiring layer, and wherein the second protective layer is disposed below the first protective layer and provides a side surface of the cavity. ### Claim 17 (depends on 12) The semiconductor package of claim 12, wherein the first connection pads of the semiconductor chip are connected to the upper wiring layer by a wire structure, and the second connection pads of the lower semiconductor chip are connected to the lower wiring layer by a bump structure. ### Claim 18 A semiconductor package comprising: a lower substrate including a lower wiring layer; an upper substrate disposed on the lower substrate and including an upper wiring layer and a cavity that has a bottom surface facing the lower substrate; an adhesive layer disposed on the bottom surface of the cavity; a semiconductor chip having a first surface and a second surface opposite to the first surface, wherein first connection pads are disposed on the first surface of the semiconductor chip and are electrically connected to the upper wiring layer, and wherein the second surface of the semiconductor chip is attached to the adhesive layer; a lower adhesive layer attached to the first surface of the semiconductor chip; a lower semiconductor chip having a third surface and a fourth surface opposite to the third surface, wherein second connection pads are disposed on the third surface of the lower semiconductor chip and are electrically connected to the lower wiring layer, and wherein the fourth surface is attached to the lower adhesive layer; a bump structure disposed below the lower semiconductor chip and electrically connecting the second connection pads to the lower wiring layer; and a connection structure disposed between the lower substrate and the upper substrate and electrically connecting the lower wiring layer and the upper wiring layer to each other, wherein each of the bump structure and the connection structure includes a low melting point metal. ### Claim 19 (depends on 18) The semiconductor package of claim 18, wherein the low melting point metal includes tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), or alloys thereof.