# US 12,604,744 B2 · Integration of glass core into electronic substrates for fine pitch die tiling

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- Number: US 12,604,744 B2
- Document ID: US12604744B2
- Status: Granted
- Kind: B2
- Application number: 17/473,111
- Filed: 2021-09-13
- Published: 2023-03-16
- Granted: 2026-04-14
- Earliest claimed: 2021-09-13
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Jeremy D. Ecton; Brandon C. Marin; Aleksandar Aleksov; Srinivas V. Pietambaram; Leonel Arana
- Web page: https://patentgrep.com/patent/US12604744B2

## CPC

- H10W 70/435: {of insulating layers on leadframes, e.g. bridging members}
- H10W 70/685: comprising multiple insulating layers
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 70/692: Ceramics or glasses
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments disclosed herein include a package substrate. In an embodiment, the package substrate comprises a core with a first surface and a second surface, where the core comprises glass. In an embodiment, a first via is through the core, where the first via comprise a conductive material, and a film over the first surface of the core, where the film is an adhesive. In an embodiment, a second via is through the film, where the second via comprises a conductive material, where the second via contacts the first via. In an embodiment, a centerline of the second via is aligned with a centerline of the first via. In an embodiment, a buildup layer is over the film.

## Claims

### Claim 1

A package substrate, comprising:
a core with a first surface and a second surface, wherein the core comprises glass;
a first via through the core, wherein the first via comprises a conductive material;
a film over the first surface of the core, wherein the film is an adhesive;
a second via in the film, wherein the second via comprises a conductive material, wherein the second via contacts the first via, wherein the second via tapers outwardly along a direction toward the first via, and wherein the second via has a greater width greater than a width of the first via where the second via contacts the first via; and
a conductive pad in the film, the conductive pad over and coupled to the second via, the conductive pad having a width greater than the width of the first via and greater than the width of the second via, and the conductive pad having a top surface at a same level as a top surface of the film; and
a buildup layer over the film.

### Claim 2 (depends on 1)

The package substrate of claim 1, wherein a first end of the second via has a first width and a second end of the second via has a second width that is smaller than the first width, and wherein the first end is closer to the core than the second end.

### Claim 3 (depends on 1)

The package substrate of claim 1, further comprising:
a first level interconnect over the buildup layer.

### Claim 4 (depends on 3)

The package substrate of claim 3, further comprising:
a plurality of buildup layers; and
conductive routing through the buildup layers to electrically couple the first level interconnect to the first via.

### Claim 5 (depends on 4)

The package substrate of claim 4, wherein a third via in the buildup layers has a tapered profile with a narrow end and a wide end, and wherein a first distance between the narrow end and the first level interconnect is smaller than a second distance between the wide end and the first level interconnect.

### Claim 6 (depends on 3)

The package substrate of claim 3, wherein the first level interconnect is lined by an interface layer, wherein the interface layer is a dielectric.

### Claim 7 (depends on 6)

The package substrate of claim 6, wherein the first level interconnect and the interface layer are configured for hybrid bonding.

### Claim 8 (depends on 3)

The package substrate of claim 3, further comprising a solder over the first level interconnect.

### Claim 9 (depends on 1)

The package substrate of claim 1, further comprising:
a bridge embedded in the buildup layer, wherein a third surface of the bridge faces away from the core, and wherein a fourth surface of the bridge faces the core.

### Claim 10 (depends on 9)

The package substrate of claim 9, wherein a third via passes through the bridge from the third surface to the fourth surface.

### Claim 11 (depends on 10)

The package substrate of claim 10, wherein a pad is disposed over the third via on the fourth surface of the bridge.

### Claim 12 (depends on 1)

The package substrate of claim 1, wherein a thickness of the core is approximately 2 mm or less.

### Claim 13

An electronic package, comprising:
a package substrate, wherein the package substrate comprises:
a core, wherein the core comprises glass, and wherein a first via passes through the core;
a film over the core, wherein the film is an adhesive, wherein a second via is in the film, wherein the first via is in contact with the second via, wherein the second via tapers outwardly along a direction toward the first via, wherein the second via has a width greater than a width of the first via where the second via contacts the first via, and a conductive pad in the film, the conductive pad over and coupled to the second via, the conductive pad having a width greater than the width of the first via and greater than the width of the second via, and the conductive pad having a top surface at a same level as a top surface of the film; and
buildup layers over the film, wherein a first level interconnect is provided over the buildup layers; and
a die coupled to the package substrate by the first level interconnect.

### Claim 14 (depends on 13)

The electronic package of claim 13, wherein the first level interconnect comprises a hybrid bond with the die.

### Claim 15 (depends on 13)

The electronic package of claim 13, wherein the first level interconnect comprises a solder.

### Claim 16 (depends on 13)

The electronic package of claim 13, wherein the second via is tapered with a wide end and a narrow end, and wherein a first distance between the wide end and the core is smaller than a second distance between the narrow end and the core.

### Claim 17 (depends on 16)

The electronic package of claim 16, wherein the wide end of the second via is wider than a width of the first via.

### Claim 18 (depends on 17)

The electronic package of claim 17, wherein a centerline of the first via is aligned with a centerline of the second via.

### Claim 19 (depends on 13)

The electronic package of claim 13, further comprising:
a bridge embedded in the buildup layers, wherein the bridge electrically couples the die to a second die.

### Claim 20 (depends on 13)

The electronic package of claim 13, wherein a third via in the buildup layers has a tapered profile with a narrow end and a wide end, and wherein a first distance between the narrow end and the first level interconnect is smaller than a second distance between the wide end and the first level interconnect.

### Claim 21

An electronic system, comprising:
a board;
a package substrate coupled to the board, wherein the package substrate comprises:
a core, wherein the core comprises glass;
a film over the core, wherein the film is an adhesive; and
buildup layers over the film, wherein a first via passes through the core and a second via is in the film, wherein the first via is in contact with the second via, wherein the second via tapers outwardly along a direction toward the first via, wherein the second via has a width greater than a width of the first via where the second via contacts the first via, and a conductive pad is in the film, the conductive pad over and coupled to the second via, the conductive pad having a width greater than the width of the first via and greater than the width of the second via, and the conductive pad having a top surface at a same level as a top surface of the film; and
a die coupled to the package substrate.

### Claim 22 (depends on 21)

The electronic system of claim 21, wherein the die is coupled to the buildup layers by a hybrid bond.

### Claim 23 (depends on 21)

The electronic system of claim 21, wherein the die is coupled to the buildup layers by a solder interconnect.