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US 12,604,741 B2Granted
Deep trench capacitor (DTC) region in semiconductor package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorFu-Chiang Kuo
Life of this patent
Estimating the term…
Abstract
A semiconductor structure is provided. The semiconductor structure includes a substrate and a deep trench capacitor (DTC) region formed in the substrate. The DTC region includes a plurality of DTC units, and each DTC unit includes: a trench extending downwardly from a top surface of the substrate; a first conductive layer disposed in the trench; a second conductive layer disposed in the trench; and a dielectric layer sandwiched by the first conductive layer and the second conductive layer. Each DTC unit is elongated, and a first group of the plurality of DTC units extend horizontally in a first direction, whereas a second group of the plurality of the DTC units extend horizontally in a second direction.
Claims20
A semiconductor structure comprising:
- a substrate of an interposer, the interposer being configured to increase interconnect density for a plurality of chips bonded to the interposer;
- and
- a deep trench capacitor (DTC) region formed in the substrate of the interposer, wherein the DTC region comprises a plurality of DTC units, each DTC unit comprises:
- a trench extending downwardly from a top surface of the substrate of the interposer;
- a first conductive layer disposed in the trench;
- a second conductive layer disposed in the trench;
- and
- a dielectric layer sandwiched by the first conductive layer and the second conductive layer;
- and
- wherein each DTC unit is elongated, a first group of the plurality of DTC units extend horizontally in a first direction, a second group of the plurality of the DTC units extend horizontally in a second direction;
- wherein the plurality of DTC units are divided into a plurality of DTC zones, each of the plurality of DTC zones corresponding to and electrically connected to one of the plurality of chips, and the plurality of chips are horizontally distributed on a top surface of the interposer;
- wherein a boundary of at least one of the plurality of DTC zones crosses a boundary of a particular group of the plurality of DTC units, such that a first portion of the particular group is included in a first DTC zone and a second portion of the particular group is included in a second DTC zone.
9 more elements
A semiconductor package comprising:
- an interposer comprising:
- a substrate;
- a multilayer interconnect (MLI) structure formed on the substrate;
- and
- a deep trench capacitor (DTC) region formed in the substrate, wherein the DTC region comprises a plurality of DTC units, each DTC unit comprises:
- a trench extending downwardly from a top surface of the substrate;
- a first conductive layer disposed in the trench;
- a second conductive layer disposed in the trench;
- and
- a dielectric layer sandwiched by the first conductive layer and the second conductive layer;
- and
- a plurality of chips bonded to and horizontally distributed on a top surface of the MLI structure of the interposer;
- wherein each of the plurality of DTC units is elongated, a first group of the plurality of DTC units extend horizontally in a first direction, a second group of the plurality of the DTC units extend horizontally in a second direction;
- wherein the plurality of DTC units are divided into a plurality of DTC zones, each of the plurality of DTC zones being electrically connected through the MLI structure to a corresponding one of the plurality of chips;
- wherein a boundary of at least one of the plurality of DTC zones crosses a boundary of a particular group of the plurality of DTC units, such that a first portion of the particular group is included in a first DTC zone and a second portion of the particular group is included in a second DTC zone.
12 more elements
A method comprising:
- providing a substrate of an interposer, the interposer being configured to increase interconnect density for a plurality of chips bonded to the interposer;
- forming a first group of trenches in the substrate of the interposer, each of the first group of trenches extending horizontally in a first direction;
- forming a second group of trenches in the substrate of the interposer, each of the second group of trenches extending horizontally in a second direction different than the first direction;
- forming a first conductive layer in each of the first group of trenches and the second group of trenches;
- forming a dielectric layer over the first conductive layer in each of the first group of trenches and the second group of trenches;
- forming a second conductive layer over the dielectric layer in each of the first group of trenches and the second group of trenches to form a plurality of deep trench capacitor (DTC) units;
- and
- bonding a plurality of chips to a top surface of interposer, wherein the plurality of chips are horizontally distributed on the top surface of the interposer;
- and
- wherein the plurality of DTC units are divided into a plurality of DTC zones, each of the plurality of DTC zones corresponding to and electrically connected to one of the plurality of chips, and the plurality of chips are horizontally distributed on a top surface of the interposer;
- wherein a boundary of at least one of the plurality of DTC zones crosses a boundary of a particular group of the plurality of DTC units, such that a first portion of the particular group is included in a first DTC zone and a second portion of the particular group is included in a second DTC zone.
8 more elements
Dependencies are inferred from the claim text.