# US 12,604,734 B2 · Integrated circuit packages and methods

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- Number: US 12,604,734 B2
- Document ID: US12604734B2
- Status: Granted
- Kind: B2
- Application number: 18/151,545
- Filed: 2023-01-09
- Published: 2024-07-11
- Granted: 2026-04-14
- Earliest claimed: 2023-01-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Che Chiang; Yuan Sheng Chiu; Hong-Yu Guo; Hsin-Yu Pan; Tsung-Shu Lin
- Web page: https://patentgrep.com/patent/US12604734B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/30: Die-attach connectors
- H10W 72/851: {Dispositions of multiple connectors or interconnections}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/90: Bond pads, in general
- H10W 72/926: {Multiple bond pads having different sizes}
- H10W 72/941: {Dispositions of bond pads}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/963: {Providing mechanical bonding or support, e.g. dummy bond pads}
- H10W 72/967: {Multiple bond pads having different functions}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/792: {between multiple chips}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.

## Claims

### Claim 1

A semiconductor package comprising:
an integrated circuit package component on a substrate, wherein the integrated circuit package component comprises an integrated circuit die;
an underfill between the integrated circuit package component and the substrate; and
a stiffener ring attached to the substrate, wherein the stiffener ring encircles the integrated circuit package component and the underfill in a top-down view, wherein the stiffener ring has a first side and a second side intersecting to form a corner region, wherein the stiffener ring comprises a perforated region in the corner region in the top-down view, wherein the perforated region comprises an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring, and wherein the array of openings comprises a plurality of columns of openings and a plurality of rows of openings.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein the stiffener ring is attached to the substrate by an adhesive, and wherein the array of openings exposes the adhesive in the top-down view.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, wherein the stiffener ring has a first width along the first side and a second width along the second side, and wherein a first length of the perforated region along the first side is greater than the second width.

### Claim 4 (depends on 3)

The semiconductor package of claim 3, wherein a second length of the perforated region along the second side is equal to the first width.

### Claim 5 (depends on 1)

The semiconductor package of claim 1, wherein the stiffener ring has a first length along the first side, and wherein a length of the perforation region along the first side is smaller than or equal to 30% of the first length.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein the perforated region has a shape of a bracket.

### Claim 7 (depends on 6)

The semiconductor package of claim 6, wherein a length of the perforation region extending along the first side is smaller than or equal to 30% of a length of the first side and wherein a length of the perforation region extending along the second side is smaller than or equal to 30% of a length of the second side.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein the stiffener ring comprises a metallic material.

### Claim 9

A semiconductor package comprising:
a substrate;
a package component bonded to the substrate by electrical connectors, the package component comprising:
an integrated circuit die;
an encapsulant around the integrated circuit die; and
a semiconductor substrate over the integrated circuit die and the encapsulant;
an underfill between the substrate and the package component, wherein the underfill surrounds the electrical connectors; and
a frame structure attached to the substrate, wherein the frame structure encircles the package component in a top-down view, wherein the frame structure comprises a perforated region at each corner of the frame structure in the top-down view, and wherein each perforated region comprises a first perforation extending through a thickness of the frame structure.

### Claim 10 (depends on 9)

The semiconductor package of claim 9, wherein each perforated region has a shape of an “L”.

### Claim 11 (depends on 9)

The semiconductor package of claim 9, wherein the first perforation has a shape of a polygon in the top-down view.

### Claim 12 (depends on 9)

The semiconductor package of claim 9, wherein the first perforation has a shape of an ellipse in the top-down view.

### Claim 13 (depends on 9)

The semiconductor package of claim 9, wherein each perforated region comprises an array of first perforations.

### Claim 14 (depends on 9)

The semiconductor package of claim 9, wherein the frame structure is attached to the substrate by an adhesive, and wherein the first perforation exposes the adhesive in the top-down view.

### Claim 15

A method of forming a semiconductor package, the method comprising:
bonding a first side of a package component to a substrate;
forming an underfill between the package component and the substrate; and
attaching a ring structure to the substrate using an adhesive, wherein the ring structure encircles the package component in a top-down view, wherein a first opening is disposed in a first perforated region of the ring structure, wherein the first opening exposes a portion of the adhesive in the top-down view, and wherein the first perforated region is disposed in a first corner region of the ring structure.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first opening extends in a direction perpendicular to the substrate.

### Claim 17 (depends on 15)

The method of claim 15, wherein sidewalls of the ring structure are free of indentations.

### Claim 18 (depends on 15)

The method of claim 15, wherein the ring structure comprises a metallic material.

### Claim 19 (depends on 15)

The method of claim 15, wherein the ring structure comprises a second opening disposed in a second perforated region of the ring structure, and wherein the second perforated region is disposed in a second corner region of the ring structure.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first perforated region and the second perforated region are on a first side of the ring structure, wherein a distance between the first perforated region and the second perforated region is larger than or equal to 40% of a length of the first side of the ring structure.