# US 12,604,732 B2 · Power electronics carrier

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- Number: US 12,604,732 B2
- Document ID: US12604732B2
- Status: Granted
- Kind: B2
- Application number: 17/186,224
- Filed: 2021-02-26
- Published: 2022-09-01
- Granted: 2026-04-14
- Earliest claimed: 2021-02-26
- Assignees: Infineon Technologies Austria AG
- Applicants: Infineon Technologies Austria AG
- Inventors: Alexander Roth; Richard Knipper
- Web page: https://patentgrep.com/patent/US12604732B2

## CPC

- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 40/778: {in encapsulations}
- H10W 70/02: of conductive package substrates serving as an interconnection, e.g. of metal plates (manufacture or treatment of leadframes H10W70/04)
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 90/00: Package configurations
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/753: {between laterally-adjacent chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A power electronics device comprises a power electronics carrier includes a non-corrosive metal substrate and a region of electrical isolation material that forms a direct interface with the metal substrate, and a first semiconductor die mounted on the region of electrical isolation material, and a coefficient of thermal expansion of the region of electrical isolation material substantially matches a coefficient of thermal expansion of metal from the metal substrate at the direct interface.

## Claims

### Claim 1

A power electronics device, comprising:
a power electronics carrier comprising a metal substrate that is non-corrosive and a region of electrical isolation material that forms a direct interface with the metal substrate;
and
a first semiconductor die mounted on the region of electrical isolation material, and
wherein the region of electrical isolation material is a layer of glass that is disposed at the direct interface with the metal substrate, and
wherein the non-corrosive metal substrate comprises steel, and
wherein a coefficient of thermal expansion of the region of electrical isolation material substantially matches a coefficient of thermal expansion of metal from the metal substrate at the direct interface.

### Claim 2 (depends on 1)

The power electronics device of claim 1, wherein the metal from the metal substrate at the direct interface is steel.

### Claim 3 (depends on 1)

The power electronics device of claim 1, further comprising a first bond pad disposed on the region of electrical isolation material, and wherein the first semiconductor die is mounted on the first bond pad.

### Claim 4 (depends on 3)

The power electronics device of claim 3, further comprising a second semiconductor die mounted on the power electronics carrier, and wherein the second semiconductor die is electrically isolated from the first semiconductor die by the region of electrical isolation material.

### Claim 5 (depends on 4)

The power electronics device of claim 4, wherein the second semiconductor die is a power transistor, and wherein the first semiconductor die is a logic device that is configured to control the power transistor.

### Claim 6 (depends on 1)

The power electronics device of claim 1, further comprising an encapsulant body of electrically insulating material that encapsulates the first semiconductor die.

### Claim 7 (depends on 6)

The power electronics device of claim 6, further comprising a first lead that is electrically connected to the first semiconductor die and is exposed from the encapsulant body, and wherein the metal substrate and the first lead are constituent parts of a steel lead frame.

### Claim 8 (depends on 6)

The power electronics device of claim 6, wherein a lower surface of the metal substrate that is opposite from the first semiconductor die is exposed from the encapsulant body.

### Claim 9 (depends on 1)

The power electronics device of claim 1, wherein the layer of glass is a layer of any one of: quartz glass, silica glass, soda lime glass, photostructurable glass, float glass, polymer glass, acrylic glass, polycarbonate, and polyethylene terephthalate.

### Claim 10

A power electronics carrier, comprising:
a metal substrate that is non-corrosive; and
a region of electrical isolation material that forms a direct interface with the metal substrate, and
wherein a coefficient of thermal expansion of the region of electrical isolation material substantially matches a coefficient of thermal expansion of the metal of the metal substrate at the direct interface; and
wherein the region of electrical isolation material is a layer of glass that is disposed at the direct interface with the metal substrate.

### Claim 11 (depends on 10)

The power electronics carrier of claim 10, wherein the metal at the direct interface comprises steel.

### Claim 12 (depends on 10)

The power electronics device of claim 10, wherein the layer of glass is a layer of any one of: quartz glass, silica glass, soda lime glass, photostructurable glass, float glass, polymer glass, acrylic glass, polycarbonate, and polyethylene terephthalate.