Chip packaging structure and preparation method therefor

Abstract

Provided in the present application are a chip packaging structure and a preparation method therefor. The chip packaging structure comprises a substrate, a chip, an insulating layer, a capacitor structure and a packaging layer. According to the chip packaging structure and the packaging method therefor provided in the present application, a capacitor structure is packaged on a surface and a lateral wall of a chip, such that the capacitor structure is applied in packaging, thereby improving the level of integration of the chip. In the present application, a first electrode layer, a second electrode layer and a capacitive dielectric layer all extend along a surface on a side of a chip facing away from a substrate and along a lateral wall of the chip. Therefore, a larger relative area of the first electrode layer and the second electrode layer can be obtained, which can improve the capacity of a capacitor.

Dependencies are inferred from the claim text.