# US 12,604,728 B2 · Integrated circuit (IC) die comprising galvanic isolation capacitor

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,604,728 B2
- Document ID: US12604728B2
- Status: Granted
- Kind: B2
- Application number: 17/936,316
- Filed: 2022-09-28
- Published: 2023-11-16
- Granted: 2026-04-14
- Earliest claimed: 2022-05-13
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Elizabeth Stewart; Jeffrey Alan West; Byron Williams; Pijush Kanti Ghosh
- Web page: https://patentgrep.com/patent/US12604728B2

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/50: Bond wires
- H10W 90/00: Package configurations
- H10W 90/293: {characterised by non-galvanic coupling between the chips, e.g. capacitive coupling}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/07554: {changes in dispositions}
- H10W 90/753: {between laterally-adjacent chips}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure generally relates to a capacitor on an integrated circuit (IC) die. In an example, a package includes first and second IC dice. The first IC die includes a first circuit, a capacitor, and a polyimide layer. The first circuit is on a substrate. The capacitor includes a bottom plate over the substrate and a top plate over the bottom plate. The polyimide layer is at least partially over the top plate. A distance from a top surface of the top plate to a bottom surface of the polyimide layer is at least 30% of a distance from a top surface of the bottom plate to a bottom surface of the top plate. A signal path, including the capacitor, is electrically coupled between the first circuit and a second circuit in the second IC die, which does not include a galvanic isolation capacitor in the signal path.

## Claims

### Claim 1

An integrated circuit (IC) package comprising:
a first IC die comprising:
a first circuit disposed on a first semiconductor substrate;
a capacitor comprising:
a bottom plate disposed over the first semiconductor substrate; and
a top plate disposed over the bottom plate, a first distance being from a top surface of the bottom plate to a bottom surface of the top plate; and
a polyimide layer disposed at least partially over the top plate of the capacitor, a second distance being from a top surface of the top plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance; and
a second IC die comprising a second circuit disposed on a second semiconductor substrate, a signal path being electrically coupled between the first circuit and the second circuit, the signal path including the capacitor, the second IC die not including a galvanic isolation capacitor in the signal path,
wherein the first distance is equal to or greater than 15 μm.

### Claim 2 (depends on 1)

The IC package of claim 1, wherein the first IC die further comprises:
an over-layer dielectric disposed at least partially over the top plate of the capacitor, the top plate of the capacitor being disposed in an uppermost metal level distal from the first semiconductor substrate;
one or more buffer dielectric layers disposed over the over-layer dielectric; and
a passivation dielectric layer disposed over the one or more buffer dielectric layers, the polyimide layer being disposed over the passivation dielectric layer.

### Claim 3 (depends on 2)

The IC package of claim 2, wherein a buffer dielectric layer of the one or more buffer dielectric layers has a dielectric constant value of 3.9 or less.

### Claim 4 (depends on 2)

The IC package of claim 2, wherein the one or more buffer dielectric layers comprises:
a first dielectric layer disposed over the over-layer dielectric;
a second dielectric layer disposed over the first dielectric layer; and
a third dielectric layer disposed over the second dielectric layer, the passivation dielectric layer being disposed over the third dielectric layer.

### Claim 5 (depends on 4)

The IC package of claim 4, wherein:
the first dielectric layer is a first layer of tetraethyl orthosilicate (TEOS);
the second dielectric layer is a second layer of TEOS; and
the third dielectric layer is a layer of silicon oxynitride.

### Claim 6 (depends on 4)

The IC package of claim 4, wherein:
the first dielectric layer is a first layer of tetraethyl orthosilicate (TEOS);
the second dielectric layer is a second layer of TEOS; and
the third dielectric layer is a third layer of TEOS.

### Claim 7 (depends on 1)

The IC package of claim 1 further comprising a wire bonded to the first IC die and the second IC die, the wire being bonded to the top plate of the capacitor through the polyimide layer, the signal path including the wire.

### Claim 8

A method of semiconductor processing, the method comprising:
forming a first capacitor plate on a first interlayer dielectric (ILD), the first ILD being disposed over a semiconductor substrate;
forming a second capacitor plate on a second ILD, the second ILD being disposed over the first capacitor plate and the first ILD, a first distance being from a top surface of the first capacitor plate to a bottom surface of the second capacitor plate, the first distance being equal to or greater than 15 μm; and
forming a polyimide layer over the second capacitor plate and the second ILD, a second distance being from a top surface of the second capacitor plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance.

### Claim 9 (depends on 8)

The method of claim 8 further comprising:
forming an over-layer dielectric over the second ILD and at least partially over the second capacitor plate, the second capacitor plate being disposed in an uppermost metal level distal from the semiconductor substrate;
forming one or more buffer dielectric layers over the over-layer dielectric; and
forming a passivation dielectric layer over the one or more buffer dielectric layers, the polyimide layer being disposed over the passivation dielectric layer.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the one or more buffer dielectric layers comprises:
forming a first dielectric layer over the over-layer dielectric;
forming a second dielectric layer over the first dielectric layer; and
forming a third dielectric layer over the second dielectric layer, the passivation dielectric layer being disposed over the third dielectric layer.

### Claim 11 (depends on 8)

The method of claim 8, wherein the second distance is equal to or greater than 32% of the first distance.

### Claim 12 (depends on 8)

The method of claim 8, wherein the second distance is in a range from 30% to 38% of the first distance.

### Claim 13 (depends on 8)

The method of claim 8 further comprising bonding a wire to the second capacitor plate through an opening through the polyimide layer.

### Claim 14

An integrated circuit (IC) die comprising:
a galvanic isolation capacitor comprising:
a bottom plate over a semiconductor substrate; and
a top plate over the bottom plate, a first distance being from a top surface of the bottom plate to a bottom surface of the top plate, the first distance being equal to or greater than 15 μm; and
a polyimide layer over the top plate of the galvanic isolation capacitor, a second distance being from a top surface of the top plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance.

### Claim 15 (depends on 14)

The IC die of claim 14 further comprising:
a first interlayer dielectric (ILD) disposed over the semiconductor substrate, the bottom plate being disposed on the first ILD;
a second ILD disposed over the bottom plate and the first ILD, the top plate being disposed on the second ILD, the top plate being disposed in an uppermost metal level;
an over-layer dielectric disposed over the second ILD and at least partially over the top plate;
one or more buffer dielectric layers disposed over the over-layer dielectric; and
a passivation dielectric layer disposed over the one or more buffer dielectric layers, the polyimide layer being disposed over the passivation dielectric layer.

### Claim 16 (depends on 14)

The IC die of claim 14, wherein the second distance is equal to or greater than 32% of the first distance.

### Claim 17 (depends on 14)

The IC die of claim 14, wherein the second distance is equal to or greater than 37% of the first distance.

### Claim 18 (depends on 14)

The IC die of claim 14, wherein the second distance is in a range from 30% to 38% of the first distance.

### Claim 19 (depends on 14)

The IC die of claim 14, wherein a thickness of the polyimide layer is equal to or greater than 110% of the first distance.

### Claim 20

An integrated circuit (IC) package comprising:
a first IC die comprising:
a first circuit disposed on a first semiconductor substrate;
a capacitor comprising:
a bottom plate disposed over the first semiconductor substrate; and
a top plate disposed over the bottom plate, a first distance being from a top surface of the bottom plate to a bottom surface of the top plate; and
a polyimide layer disposed at least partially over the top plate of the capacitor, a second distance being from a top surface of the top plate to a bottom surface of the polyimide layer, the second distance being equal to or greater than 30% of the first distance; and
a second IC die comprising a second circuit disposed on a second semiconductor substrate, a signal path being electrically coupled between the first circuit and the second circuit, the signal path including the capacitor, the second IC die not including a galvanic isolation capacitor in the signal path, wherein the first IC die further comprises:
an over-layer dielectric disposed at least partially over the top plate of the capacitor, the top plate of the capacitor being disposed in an uppermost metal level distal from the first semiconductor substrate;
one or more buffer dielectric layers disposed over the over-layer dielectric; and
a passivation dielectric layer disposed over the one or more buffer dielectric layers, the polyimide layer being disposed over the passivation dielectric layer.