# US 12,604,727 B2 · Semiconductor chip including low-k dielectric layer

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- Number: US 12,604,727 B2
- Document ID: US12604727B2
- Status: Granted
- Kind: B2
- Application number: 18/127,342
- Filed: 2023-03-28
- Published: 2023-07-20
- Granted: 2026-04-14
- Earliest claimed: 2019-08-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yeonjin Lee; Junyong Noh; Minjung Choi; Junghoon Han; Yunrae Cho
- Web page: https://patentgrep.com/patent/US12604727B2

## CPC

- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 74/131: {the semiconductor body being only partially enclosed}
- H10D 84/01: Manufacture or treatment
- H10D 86/01: Manufacture or treatment
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/90: Bond pads, in general
- H10W 74/014: {using batch processing}
- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/69: Insulating materials thereof
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

## Claims

### Claim 1

A semiconductor chip comprising:
a substrate;
a device layer arranged on the substrate and including a plurality of semiconductor devices;
a lower inter-wiring dielectric layer arranged on the device layer and having a lower permittivity than silicon oxide;
a wiring structure in the lower inter-wiring dielectric layer;
an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer, the upper inter-wiring dielectric layer having a permittivity that is equal to or higher than a permittivity of silicon oxide;
an isolation recess arranged along an edge of the substrate, the isolation recess having a side surface that is defined by a side surface of each of the lower inter-wiring dielectric layer and the upper inter-wiring dielectric layer and a bottom surface that is defined by a top surface of the device layer, the bottom surface of the isolation recess being at a level that is equal to or lower than a level of a bottom surface of the lower inter-wiring dielectric layer;
a pad pattern arranged on the upper inter-wiring dielectric layer and electrically connected to the wiring structure; and
a cover dielectric layer including a sub cover dielectric layer and an upper cover dielectric layer,
wherein the sub cover dielectric layer covers the bottom surface of the isolation recess, the side surface of the isolation recess, a top surface of the upper inter-wiring dielectric layer, a side surface of the pad pattern and a first portion of a top surface of the pad pattern,
wherein the sub cover dielectric layer does not cover a second portion of the top surface of the pad pattern, and
wherein the upper cover dielectric layer fills the isolation recess and covers the sub cover dielectric layer.

### Claim 2 (depends on 1)

The semiconductor chip of claim 1, wherein the upper cover dielectric layer contacts the entire top surface of the sub cover dielectric layer.

### Claim 3 (depends on 1)

The semiconductor chip of claim 1,
wherein the upper cover dielectric layer includes a first portion covering the top surface of the upper inter-wiring dielectric layer, and a second portion covering the side surface of the isolation recess and the bottom surface of the isolation recess, and
wherein the upper cover dielectric layer includes a photosensitive polyimide.

### Claim 4 (depends on 3)

The semiconductor chip of claim 3, wherein the top surface of the first portion of the upper cover dielectric layer is at a higher level than the top surface of the pad pattern, and
the sub cover dielectric layer is formed of nitride.

### Claim 5 (depends on 3)

The semiconductor chip of claim 3, wherein the top surface of the first portion of the upper cover dielectric layer is at a higher level than a top surface of the sub cover dielectric layer.

### Claim 6 (depends on 1)

The semiconductor chip of claim 1, further comprising a sub pad electrically connecting the pad pattern to the wiring structure,
wherein the upper inter-wiring dielectric layer includes a first upper inter-wiring dielectric layer covering the lower inter-wiring dielectric layer, and a second upper inter-wiring dielectric layer covering the first upper inter-wiring dielectric layer and the sub pad,
wherein the sub pad is arranged on the first upper inter-wiring dielectric layer, and
wherein the second upper inter-wiring dielectric layer contacts a side surface and a top surface of the sub pad.

### Claim 7 (depends on 6)

The semiconductor chip of claim 6, wherein a top surface of the second upper inter-wiring dielectric layer that is vertically overlapped with the sub pad is higher than a top surface of the second upper inter-wiring dielectric layer that is not vertically overlapped with the sub pad.

### Claim 8 (depends on 7)

The semiconductor chip of claim 7,
wherein the upper inter-wiring dielectric layer includes a third upper inter-wiring dielectric layer covering the second upper inter-wiring dielectric layer, and a fourth upper inter-wiring dielectric layer covering the third upper inter-wiring dielectric layer, and
wherein a top surface of the third upper inter-wiring dielectric layer that is vertically overlapped with the sub pad is higher than a top surface of the third upper inter-wiring dielectric layer that is not vertically overlapped with sub pad.

### Claim 9 (depends on 8)

The semiconductor chip of claim 8, wherein a top surface of the fourth upper inter-wiring dielectric layer is substantially flat.

### Claim 10 (depends on 6)

The semiconductor chip of claim 6, wherein a thickness of the pad pattern is greater than a thickness of the sub pad.

### Claim 11

A semiconductor chip comprising:
a substrate;
a device layer arranged on the substrate and including a plurality of semiconductor devices;
a lower inter-wiring dielectric layer arranged on the device layer; a wiring structure in the lower inter-wiring dielectric layer;
an upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer;
an isolation recess arranged along an edge of the substrate and extending from a top surface of the upper inter-wiring dielectric layer at least to the same level as a bottom surface of the lower inter-wiring dielectric layer;
a pad pattern arranged on the upper inter-wiring dielectric layer and electrically connected to the wiring structure; and
a cover dielectric layer filling the isolation recess and covering at least a portion of the top surface of the upper inter-wiring dielectric layer, the cover dielectric layer having a step portion that is adjacent to a portion of the edge of the substrate,
wherein the cover dielectric layer includes a sub cover dielectric layer covering a top surface of the device layer that is exposed by the isolation recess, a side surface of the lower inter-wiring dielectric layer, a side surface of the upper inter-wiring dielectric layer, the top surface of the upper inter-wiring dielectric layer, a side surface of the pad pattern and a first portion of a top surface of the pad pattern, and
wherein the sub cover dielectric layer does not cover a second portion of the top surface of the pad pattern.

### Claim 12 (depends on 11)

The semiconductor chip of claim 11, wherein the isolation recess extends below the bottom surface of the lower inter-wiring dielectric layer and extends in the device layer.

### Claim 13 (depends on 11)

The semiconductor chip of claim 11,
wherein the cover dielectric layer includes an upper cover dielectric layer filling the isolation recess and covering the sub cover dielectric layer,
wherein the upper cover dielectric layer includes a photosensitive polyimide, and
wherein an uppermost surface of the upper cover dielectric layer is at a higher level than an uppermost surface of the sub cover dielectric layer.

### Claim 14 (depends on 13)

The semiconductor chip of claim 13, wherein an uppermost surface of the upper cover dielectric layer is at a higher level than an uppermost surface of the pad pattern.

### Claim 15 (depends on 13)

The semiconductor chip of claim 13, wherein a top surface of a portion of the upper cover dielectric layer covering the top surface of the upper inter-wiring dielectric layer is substantially flat.

### Claim 16 (depends on 11)

The semiconductor chip of claim 11, further comprising a sub pad electrically connecting the pad pattern to the wiring structure,
wherein the upper inter-wiring dielectric layer includes a first upper inter-wiring dielectric layer covering the lower inter-wiring dielectric layer, a second upper inter-wiring dielectric layer covering the first upper inter-wiring dielectric layer and a side surface and a top surface of the sub pad, a third upper inter-wiring dielectric layer covering the second upper inter-wiring dielectric layer, and a fourth upper inter-wiring dielectric layer covering the third upper inter-wiring dielectric layer, and
wherein each of the second upper inter-wiring dielectric layer and the third upper inter-wiring dielectric layer has an uneven top surface, and the fourth upper inter-wiring dielectric layer has a flat top surface.

### Claim 17 (depends on 11)

The semiconductor chip of claim 11,
wherein the lower inter-wiring dielectric layer is a low-k dielectric layer having a lower permittivity than silicon oxide, and
wherein a permittivity of the upper inter-wiring dielectric layer is greater than a permittivity of the lower inter-wiring dielectric layer.

### Claim 18

A semiconductor chip comprising:
a substrate;
a device layer arranged on the substrate and including a plurality of semiconductor devices;
a lower inter-wiring dielectric layer arranged on the device layer and having a lower permittivity than silicon oxide;
a wiring structure in the lower inter-wiring dielectric layer;
a first upper inter-wiring dielectric layer on the lower inter-wiring dielectric layer;
a sub pad arranged on the first upper inter-wiring dielectric layer and electrically connected to the wiring structure;
a second upper inter-wiring dielectric layer on the first upper inter-wiring dielectric layer and the sub pad, a top surface of the second upper inter-wiring dielectric layer that is vertically overlapped with the sub pad is higher than a top surface of the second upper inter-wiring dielectric layer that is not vertically overlapped with the sub pad;
a third upper inter-wiring dielectric layer on the second upper inter-wiring dielectric layer, the third upper inter-wiring dielectric layer has a top surface that is substantially flat;
an isolation recess arranged along an edge of the substrate and extending from a top surface of the third upper inter-wiring dielectric layer at least to the same level as a bottom surface of the lower inter-wiring dielectric layer;
a pad pattern arranged on the third upper inter-wiring dielectric layer and electrically connected to the sub pad;
a sub cover dielectric layer covering a top surface of the device layer that is exposed by the isolation recess, a side surface of each of the lower inter-wiring dielectric layer and the first to third upper inter-wiring dielectric layers, the top surface of the third upper inter-wiring dielectric layer, a side surface of the pad pattern and a portion of a top surface of the pad pattern; and
an upper cover dielectric layer filling the isolation recess and covering the sub cover dielectric layer,
wherein an uppermost surface of the upper cover dielectric layer is at a higher level than an uppermost surface of the sub cover dielectric layer and an uppermost surface of the pad pattern.

### Claim 19 (depends on 18)

The semiconductor chip of claim 18, wherein a thickness of the pad pattern is greater than a thickness of the sub pad.

### Claim 20 (depends on 18)

The semiconductor chip of claim 18, further comprising a fourth upper inter-wiring dielectric layer between the second upper inter-wiring dielectric layer and the third upper inter-wiring dielectric layer,
wherein a top surface of the fourth upper inter-wiring dielectric layer that is vertically overlapped with the sub pad is higher than a top surface of the fourth upper inter-wiring dielectric layer that is not vertically overlapped with sub pad.