# US 12,604,724 B2 · Vertical semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,604,724 B2 - Document ID: US12604724B2 - Status: Granted - Kind: B2 - Application number: 18/312,880 - Filed: 2023-05-05 - Published: 2024-01-11 - Granted: 2026-04-14 - Earliest claimed: 2022-07-06 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jaeho Kim; Woosung Yang; Jimo Gu; Sukkang Sung; Ahreum Lee - Web page: https://patentgrep.com/patent/US12604724B2 ## CPC - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10B 41/10: characterised by the top-view layout - H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 41/35: with a cell select transistor, e.g. NAND - H10B 43/10: characterised by the top-view layout - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - H10B 43/35: with cell select transistors, e.g. NAND - H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions - H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass - H10W 20/42: Vias, e.g. via plugs - H10W 80/00: Direct bonding of chips, wafers or substrates - H10W 90/00: Package configurations - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A vertical semiconductor device includes lower circuit patterns disposed on a first substrate. A bonding layer is disposed on the lower circuit patterns. A wire is disposed on the bonding layer. A cell stack structure is disposed on the wire. A base pattern is disposed on the cell stack structure. An upper insulating layer is disposed on the base pattern. A cell contact plug passes through the cell stack structure and extends to the upper insulating layer. A through-plug is disposed inside a through-hole formed through an outer side of the base pattern to extend to the upper insulating layer. Each of the cell contact plug and the through-plug includes a barrier metal pattern and a metal pattern, and the barrier metal pattern is disposed along sidewalls and bottom surfaces of the cell contact hole and the through-hole. ## Claims ### Claim 1 A vertical semiconductor device, comprising: lower circuit patterns disposed on a first substrate; a bonding layer disposed on the lower circuit patterns; a wire disposed on the bonding layer; pattern structures disposed on the wire, each of the pattern structures including insulating patterns and gate electrodes, which are alternately stacked on a top surface of the first substrate in a vertical direction, the pattern structures having an edge region having a step shape in which a length gradually increases from a bottom to a top, and extending in a first direction that is parallel to the top surface of the first substrate; an embedded insulating pattern disposed inside a trench that is disposed between the pattern structures, and extending in the first direction; a base pattern disposed on the pattern structure; an upper insulating layer disposed on the base pattern; a channel structure disposed inside a channel hole formed through the pattern structure, and extending to the base pattern; a cell contact plug disposed inside a cell contact hole formed through a step-shaped region of the pattern structure, extending to the upper insulating layer, and electrically connected to one gate electrode in the pattern structure; and a through-plug disposed inside a through-hole formed through an outer side of the base pattern and extending to the upper insulating layer, wherein each of bottom surfaces of the cell contact plug and the through-plug is disposed at a level higher than a bottom surface of the embedded insulating pattern. ### Claim 2 (depends on 1) The vertical semiconductor device of claim 1, wherein each of the trench, the channel hole, the cell contact hole, and the through-hole has a sidewall inclined to have a width that gradually widens from a bottom to a top, and wherein a sidewall of each of the trench, the channel hole, the cell contact hole, and the through-hole has a bent part. ### Claim 3 (depends on 2) The vertical semiconductor device of claim 2, wherein the bent parts of the trench, the channel hole, the cell contact hole, and the through-hole are disposed on a same plane. ### Claim 4 (depends on 1) The vertical semiconductor device of claim 1, wherein the cell contact plug and the through-plug include a same metal pattern, and wherein a seam is included inside the metal pattern. ### Claim 5 (depends on 1) The vertical semiconductor device of claim 1, wherein each of the cell contact plug and the through-plug includes a barrier metal pattern and a metal pattern, and wherein the barrier metal pattern is disposed along sidewalls and bottom surfaces of the cell contact hole and the through-hole. ### Claim 6 (depends on 1) The vertical semiconductor device of claim 1, wherein the wire includes a contact plug, and wherein a barrier metal pattern included in each of the cell contact plug and the through-plug makes direct contact with the contact plug. ### Claim 7 (depends on 1) The vertical semiconductor device of claim 1, further comprising a plate contact plug disposed inside a plate contact hole formed through an outer side of the pattern structure, and electrically connected to the base pattern. ### Claim 8 (depends on 7) The vertical semiconductor device of claim 7, wherein bottom surfaces of the cell contact plug, the through-plug, and the plate contact plug are disposed on a same plane. ### Claim 9 (depends on 8) The vertical semiconductor device of claim 8, wherein the bottom surfaces of the cell contact plug, the through-plug, and the plate contact plug are disposed on a plane between a bottom surface of the channel structure and the bottom surface of the embedded insulating pattern. ### Claim 10 (depends on 7) The vertical semiconductor device of claim 7, wherein the plate contact plug passes through the base pattern and contacts the upper insulating layer. ### Claim 11 (depends on 7) The vertical semiconductor device of claim 7, wherein the plate contact plug contacts a bottom surface of the base pattern without passing through the base pattern. ### Claim 12 (depends on 1) The vertical semiconductor device of claim 1, wherein each of uppermost portions of the cell contact plug and the through-plug has an inclination so that a width gradually decreases from a top to a bottom. ### Claim 13 (depends on 1) The vertical semiconductor device of claim 1, further comprising a dummy structure passing through the step-shaped region of the pattern structure and extending to a bottom surface of the base pattern. ### Claim 14 A vertical semiconductor device, comprising: lower circuit patterns disposed on a first substrate; a bonding layer disposed on the lower circuit patterns; a wire disposed on the bonding layer; pattern structures disposed on the wire, each of the pattern structures including insulating patterns and gate electrodes, which are alternately stacked on a top surface of the first substrate in a vertical direction, the pattern structures having an edge region having a step shape in which a length gradually increases from a bottom to a top, and extending in a first direction that is parallel to the top surface of the first substrate; a base pattern disposed on the pattern structure; an upper insulating layer on the base pattern; a channel structure disposed inside a channel hole formed through the pattern structure, and extending to the base pattern; a cell contact plug disposed inside a cell contact hole formed through a step-shaped region of the pattern structure, extending to the upper insulating layer, and electrically connected to one gate electrode in the pattern structure; a through-plug disposed inside a through-hole formed through an outer side of the base pattern to extend to the upper insulating layer; and a plate contact plug disposed inside a plate contact hole formed through an outer side of the pattern structure, and electrically connected to the base pattern, wherein bottom surfaces of the cell contact plug, the through-plug, and the plate contact plug are disposed on a same plane. ### Claim 15 (depends on 14) The vertical semiconductor device of claim 14, further comprising an embedded insulating pattern disposed inside a trench that is disposed between the pattern structures, and extending in the first direction, wherein each of the bottom surfaces of the cell contact plug, the through-plug, and the plate contact plug is disposed at a level higher than a bottom surface of the embedded insulating pattern. ### Claim 16 (depends on 14) The vertical semiconductor device of claim 14, wherein each of the channel hole, the cell contact hole, the through-hole, and the plate contact hole has a sidewall inclination to have a width that gradually widens from a bottom to a top, and wherein a sidewall of each of the channel hole, the cell contact hole, the through-hole, and the plate contact hole has a bent part. ### Claim 17 (depends on 14) The vertical semiconductor device of claim 14, wherein the bent parts of the channel hole, the cell contact hole, the through-hole, and the plate contact hole are disposed on a same plane. ### Claim 18 (depends on 14) The vertical semiconductor device of claim 14, wherein each of the cell contact plug, the through-plug, and the plate contact plug includes a barrier metal pattern and a metal pattern, and wherein the barrier metal pattern is disposed along sidewalls and bottom surfaces of the cell contact hole, the through-hole, and the plate contact hole. ### Claim 19 A vertical semiconductor device, comprising: lower circuit patterns disposed on a first substrate; a bonding layer disposed on the lower circuit patterns; a wire disposed on the bonding layer; a cell stack structure disposed on the wire; a base pattern disposed on the cell stack structure; an upper insulating layer disposed on the base pattern; a cell contact plug passing through the cell stack structure and extending to the upper insulating layer; and a through-plug disposed inside a through-hole formed through an outer side of the base pattern to extend to the upper insulating layer, wherein each of the cell contact plug and the through-plug includes a barrier metal pattern and a metal pattern, and wherein the barrier metal pattern is disposed along sidewalls and bottom surfaces of the cell contact hole and the through-hole. ### Claim 20 (depends on 19) The vertical semiconductor device of claim 19, further comprising a plate contact plug disposed inside a plate contact hole formed through an outer side of the pattern structure, and electrically connected to the base pattern.