# US 12,604,723 B2 · Metal capping layer for reducing gate resistance in semiconductor devices

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- Number: US 12,604,723 B2
- Document ID: US12604723B2
- Status: Granted
- Kind: B2
- Application number: 17/738,238
- Filed: 2022-05-06
- Published: 2023-01-19
- Granted: 2026-04-14
- Earliest claimed: 2021-07-09
- Assignees: Taiwan Semicondictor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Wei-Cheng Wang; Shih-Hang Chiu; Kuan-Ting Liu; Chi On Chui; Chia-Wei Chen; Jian-Hao Chen
- Web page: https://patentgrep.com/patent/US12604723B2

## CPC

- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 64/01: Manufacture or treatment
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/46: comprising air gaps
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10W 20/033: {in openings in dielectrics}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a semiconductor fin protruding from a substrate;
a gate structure engaging with the semiconductor fin;
an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, wherein a top surface of the gate structure is below a top surface of the ILD layer;
a first metal layer in direct contact with the top surface of the gate structure, wherein a middle portion of a bottom surface of the first metal layer is lower than a side portion of the bottom surface of the first metal layer;
a second metal layer disposed over the first metal layer, wherein the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, wherein the bottom surface of the second metal layer has a curved profile, wherein a topmost surface of the first metal layer is away from a top surface of the second metal layer, and wherein the second metal layer differs from the first metal layer in composition; and
a gate contact disposed over the second metal layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a top surface of the second metal layer has a convex profile.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, further comprising a second ILD layer disposed over the second metal layer, wherein a portion of the second ILD layer is sandwiched between the first metal layer and the second metal layer.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the first metal layer and the bottom surface of the second metal layer form an angle that is greater than 0 degree and less than 50 degrees.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the first metal layer includes TiN, TaN, or a combination thereof,
wherein the first metal layer has a top surface and the bottom surface curved toward a same direction.

### Claim 6 (depends on 1)

The semiconductor structure of claim 1, wherein the second metal layer includes tungsten (W).

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, further comprising:
a dielectric layer disposed around the gate contact, and
an air gap disposed between a sidewall of the first metal layer and a sidewall of the second metal layer, wherein the dielectric layer is exposed to the air gap.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, at least a portion of the top surface of the second metal layer is coplanar with the top surface of the ILD layer.

### Claim 9

A semiconductor structure, comprising:
a fin extending from a semiconductor substrate;
a gate stack disposed over a channel region of the fin;
a glue layer in contact with a top surface of the gate stack;
a tungsten (W)-containing capping layer disposed over the glue layer, wherein the glue layer surrounds bottom and sidewall surfaces of the W-containing capping layer; and
a contact feature disposed on a top surface of the W-containing capping layer,
wherein the glue layer and the W-containing capping layer sandwich an air gap.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the fin includes a plurality of semiconductor layers, and wherein a bottom portion of the gate stack is interleaved with the plurality of semiconductor layers.

### Claim 11 (depends on 9)

The semiconductor structure of claim 9, wherein the W-containing capping layer and the gate stack both include fluorine (F) atoms.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein the gate stack includes aluminum (Al), and wherein the F atoms selectively bond with the Al in the gate stack.

### Claim 13 (depends on 9)

The semiconductor structure of claim 9, wherein a thickness of the glue layer is less than a thickness of the W-containing capping layer.

### Claim 14 (depends on 9)

The semiconductor structure of claim 9, wherein the top surface of the W-containing capping layer is curved,
wherein a top surface of the glue layer is higher than a portion of the top surface of the W-containing capping layer.

### Claim 15 (depends on 9)

The semiconductor structure of claim 9, further comprising:
an interlayer dielectric (ILD) layer over the W-containing capping layer, wherein the contact feature is disposed in the ILD layer; and
an air gap enclosed by the ILD layer, the glue layer, and the W-containing capping layer.

### Claim 16

A semiconductor structure, comprising:
a semiconductor active region;
a gate structure disposed over the semiconductor active region;
a gate spacer disposed along a sidewall of the gate structure;
a glue layer disposed on a top surface of the gate structure and interfacing the gate spacer;
a metal capping layer disposed over the glue layer and spaced apart from the gate spacer by the glue layer; and
a gate contact disposed over the metal capping layer,
wherein a first top surface and a bottom surface of the glue layer are curved toward a first direction,
wherein a top surface of the metal capping layer is curved toward a second direction opposite to the first direction,
wherein the top surface of the metal capping layer includes a middle portion and two side portions on two sides of the middle portion,
wherein the middle portion interfaces with the gate contact, and the two side portions are spaced apart from and at a level lower than a bottom surface of the gate contact.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, further comprising an interlayer dielectric (ILD) layer disposed over the metal capping layer and adjacent to the gate contact,
wherein a portion of the ILD layer extends to below a second top surface of the glue layer and be between the glue layer and the metal capping layer.

### Claim 18 (depends on 16)

The semiconductor structure of claim 16, wherein a second top surface of the glue layer is above at least a portion of a top surface of the meta capping layer,
wherein the second top surface of the glue layer is discontinuous from the first top surface of the glue layer.

### Claim 19 (depends on 16)

The semiconductor structure of claim 16, further comprising a dielectric layer sandwiched between a top surface of the metal capping layer and a bottom surface of the gate contact.

### Claim 20 (depends on 16)

The semiconductor structure of claim 16, wherein a second top surface of the glue layer has a flat profile and interfaces with a dielectric layer.